Shilei Hao

A 10 GHz delay line frequency discriminator and PD/CP based CMOS phase noise measurement circuit with −138.6 dBc/Hz sensitivity at 1 MHz offset

This paper presents a delay line frequency discriminator (FD) and phase detector (PD)/charge pump (CP) based phase noise measurement (PNM) circuit to achieve wide bandwidth, great sensitivity and reliable integration at 10 GHz. PD/CP based phase noise detection makes it insensitive to environment and coupling noises. A delay-locked loop (DLL) is designed to align the PD input phases and a DC offset cancellation circuit is embedded to overcome circuit mismatches, which make the PNM self-calibrated. This PNM demonstrates -61/-81 dBc single tone sensitivity and -110.35/-138.60 dBc/Hz phase noise sensitivity at 100 kHz/1 MHz offset, respectively. The phase noise measurement bandwidth is 200 MHz, which is determined by the off-chip SAW filter bandwidth. This proof-of-concept design is fabricated in a 65 nm CMOS technology with the chip area of 1.5 mm × 1.3 mm. The core circuit consumes 15.2 mW power.

A 10 GHz phase noise filter with 10.6 dB phase noise suppression and −116 dBc/Hz sensitivity at 1 MHz offset

This paper presents a phase noise filter technique enabled by the delay-line and PD/CP based frequency discriminator with fully automatic calibration. It features wide bandwidth and insensitivity to amplitude noise. At low/high gain mode, it achieves 10.6/15 dB phase noise suppression with -116/-114.9 dBc/Hz sensitivity at 1 MHz offset, respectively. The suppression bandwidth is 100 kHz-10 MHz with input operating frequency range of 9.99-10.10 GHz. This proof-of-concept design is fabricated in a 65 nm CMOS process with the chip area of 1.68 mm × 1.5 mm. The circuit consumes 102 mW power.

A 10.01–10.1 GHz bang-bang PD based phase noise filter with 12.6 dB noise suppression

In this paper, a bang-bang phase detector (BBPD) and delay-line frequency discriminator (FD) based phase noise filter (PNF) is presented. With a large gain, BBPD based PNF enhances PNF sensitivity by suppressing charge pump noise. Moreover, the proposed BBPD based PNF features wide noise suppression bandwidth and wide input frequency range. At 1 MHz offset, the PNF demonstrates 12.6 dB phase noise suppression with -117.2 dBc/Hz sensitivity. The PN suppression offset frequency is from 100 KHz to 8 MHz with 10.01-10.1 GHz input frequency range. The chip was fabricated in a 65 nm CMOS technology.

A fourth order tunable capacitor coupled microstrip resonator band pass filter

This paper presents a simple and efficient tunable microstrip band pass filter based on the reflected group delay method. The effect of varactor location on the filter performance is investigated in details to guide the filter design. The measured results are consistent with both analytical and simulation results.

A bang-bang PD based phase noise filter with 23 dB noise suppression

In this paper, we present a bang-bang phase detector (BBPD) and delay-line frequency discriminator (FD) based phase noise filter (PNF). With a larger phase detection gain, the BBPD based PNF enhances the phase noise cancellation and sensitivity by suppressing the charge pump (CP) noise. A time-amplifier (TA) and a 5 × voting machine are introduced together with the modified sense-amplifier-flip-flop (SAFF) to minimize the BBPD random noise. At 1 MHz offset, the maximum phase noise suppression is 23 dB and best phase noise sensitivity is −120.2 dBc/Hz. Its phase noise suppression offset frequency is from 100 kHz to 8 MHz with 100 MHz input frequency range. The circuit is fabricated in a 65 nm CMOS technology and dissipates 98 mW power.

A CMOS Phase Noise Filter With Passive Delay Line and PD/CP-Based Frequency Discriminator

A CMOS phase noise filter (PNF) enabled by the passive delay line (DL) and phase detector/charge pump (PD/CP)-based frequency discriminator is proposed. The delay-locked loop and dc offset cancellation loop are embedded in the PNF to achieve fully automatic calibration. The PNF is insensitive to the amplitude noise due to the PD/CP phase extraction feature. With a 20-ns DL, the PNF achieves 10.6/15-dB phase noise suppression with −116.6/−114.9-dBc/Hz phase noise sensitivity at 1-MHz offset in low/high-gain mode, respectively. The suppression offset frequency range is 100 kHz–12 MHz with 9.97–10.087-GHz input frequency range. The phase noise sensitivity improves to −119.9/−123.4 dBc/Hz at 1-MHz offset with the 40/80-ns DL, respectively. The integrated jitter from 10 kHz to 100 MHz is 176/111/85.5 fs with the 20/40/80-ns DL. The PNF is fabricated in a 65-nm CMOS process with the chip area of 1.68 mm

Analysis and Design of Bang-Bang PD-Based Phase Noise Filter

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Frequency discriminator based phase noise filter for high fidelity clock

mm and power consumption of 102 mW. The PNF provides a new approach to further enhance the phase noise and jitter performance especially at low offset frequencies.

Phase noise improvement for array systems

In this paper, we present a bang-bang phase detector (BBPD) and a delay-line frequency discriminator-based phase noise filter (PNF). With a larger phase detection gain, the BBPD-based PNF enhances the sensitivity by suppressing the charge pump noise. A time-amplifier and a five times voting machine are introduced together with the sense-amplifier-flip-flop to minimize the BBPD noise to make its effects negligible in the PNF sensitivity. At 1-MHz offset, the PNF demonstrates 15-dB phase noise suppression with −120.2-dBc/Hz sensitivity. Its phase noise suppression offset frequency is from 100 kHz to 8 MHz with 10–10.1-GHz input frequency range. The circuit is fabricated in a 65-nm CMOS technology, and dissipates 98-mW power.

A 10-GHz Delay Line Frequency Discriminator and PD/CP-Based CMOS Phase Noise Measurement Circuit

Low phase noise frequency source is the key block in the electronic systems. This paper reviews the recently published frequency discriminator based phase noise filter (PNF) techniques for the high fidelity clock. The proposed linear and Bang-Bang phase detector based PNFs are detailed in terms of the design concern, phase noise sensitivity improvement and advantages compared with other techniques. The proof-of-concept demonstrations achieve large phase noise suppression with good sensitivity for a 10 GHz clock. In addition, the benefit of PNF application in the array system is addressed. Outlook and future work of the PNF are also discussed.