Qun Jane Gu

A Low Phase Noise, Wideband and Compact CMOS PLL for Use in a Heterodyne 802.15.3c Transceiver

A low phase noise, wideband, mm-wave, integer-N PLL that is capable of supporting an 802.15.3c heterodyne transceiver is reported. The PLL can generate 6 equally spaced tones from 43.2 GHz to 51.84 GHz, which is suitable for a heterodyne architecture with FLO=(4/5)×FTRX. Phase noise is measured directly at the FLO frequency and is better than -97.5 dBc/Hz@1 MHz across the entire band. The reported frequency synthesizer is smaller, exhibits less phase noise, and consumes less power than prior art. In addition, the FLO tone corresponds to the fundamental of the VCO as opposed to a higher harmonic.

Two-Way Current-Combining

This paper presents a two-way current-combining-based W-band power amplifier (PA) in 65-nm CMOS technology. An analytical model and design method for W-band power combiners are presented, which indicates current combining is preferred for millimeter-wave frequencies due to a good current handling capability, symmetrical design, and low sensitivity to parasitics. To demonstrate the concept, a two-way current-combining-based PA has been fabricated, where each channel utilizes compact and symmetrical transformer-based inter-stage coupling to realize a preferred fully differential implementation. This PA operates from 101 to 117 GHz with maximum power gain of 14.1 dB, saturated output power (Psat) of 14.8 dBm, and peak power-added efficiency of 9.4%. The core chip area without pads is 0.106 mm2.

W

A dual-band direct-conversion RF transceiver for IEEE 802.11 a/b/g WLAN is implemented in 0.18 /spl mu/m CMOS technology with 6 mm/sup 2/ die size and 182 mW power dissipation while transmitting 1 dBm at 5 GHz. The receiver achieves 5 dB NF, -8 dBm IIP3 (high LNA gain), 96 dB total gain, and -31.4 dB EVM. The transmitter achieves 1 dBm and 2.5 dBm linear output power at 5 GHz and 2.4 GHz, respectively, with an EVM less than -31 dB.

-Band Power Amplifier in 65-nm CMOS

This paper reports a CMOS terahertz oscillator with a novel frequency selective negative resistance (FSNR) tank to boost its operating frequency. The demonstrated oscillator can operate at a fundamental frequency of about 0.22 THz, exceeding the CMOS device cutoff frequency of fT. The proposed architecture suppresses undesired 2nd and odd harmonics and boosts the fourth-order harmonic (0.87 THz), which radiates through an on-chip patch antenna. The THz oscillators output spectrum is profiled by using a Michelson interferometer. The oscillator circuit consumes 12 mA from a 1.4 V supply and occupies a 0.045 mm2 die area in a 65 nm CMOS technology.

A compact dual-band direct-conversion CMOS transceiver for 802.11a/b/g WLAN

Millimeter-Wave-based radar has gained attention in recent years for automotive and object detection applications. Several new applications are also emerging which employ mm-Wave radar techniques to construct short range mm-Wave 3D imaging systems for security screening and biomedical applications. At present, these types of 3D mm-Wave imagers have only been demonstrated in lll-V technology, as CMOS-based radar suffers several range and resolution limitations due to limited output power and linearity.Most CMOS mm-Wave radar systems used in automotive applications are based on Frequency-Modulated Continuous-Wave (FMCW) ranging techniques in which the carrier is swept to produce a frequency offset at the receiver output proportional to the round-trip distance between the radar and target. While FMCW is an excellent approach for accurate ranging, its implementation becomes particularly difficult at high frequencies as the resolution is heavily dependent on sweep linearity and the high RF front-end performance required to support the wideband swept carrier. For 3D mm-Wave imaging applications, this high operating frequency is indispensable as the attainable spatial (XY) resolution is fundamentally limited by the wavelength of the imaging system. Higher frequency also helps relax focusing lens requirements, as the optical diffraction limit is set by the ratio of the radar wavelength over the lens aperture size.

CMOS THz Generator With Frequency Selective Negative Resistance Tank

A W-band power amplifier (PA) has been realized in 65 nm bulk CMOS technology, which covers 100 to 117 GHz. It delivers up to 13.8 dBm saturated output power with up to 15 dB power gain and 10% PAE, which also achieves better than 10.1 dBm output P1 dB. The PA features compact realization with transformer-coupled three stages and on-chip input/output baluns to facilitate single-ended characterization. To ensure stability and boost efficiency, it adopts cascode structure in the first two stages and common source amplifier in the last stage. To improve the PAE and linearity, an adaptive biasing circuitry is incorporated inside the PA. The entire PA core occupies 0.041 mm2 die area and burns about 180 mW with the adaptive bias circuit consuming only 0.002 mm2 active chip area.

A 144GHz 0.76cm-resolution sub-carrier SAR phase radar for 3D imaging in 65nm CMOS

A 70-78-GHz integrated frequency synthesizer is implemented in 65-nm CMOS. It has been integrated in a two-step zero-IF millimeter-wave transceiver for emerging applications, such as 81-86-GHz satellite communication, short-distance high-speed wireless link, as well as imaging and radar. The transceiver utilizes synthesizer voltage-controlled oscillator (VCO) output as the first LORF and 1/8 of LORF as the second LORF to cover the desired frequency band. The proposed synthesizer adopts integer-N architecture with 50-MHz reference. It also features coarse phase rotation to provide beam-forming capability for the intended transceiver. The synthesizer phase noise (PN) has been measured at 1/8 of the VCO frequency, about -102.2 dBc/Hz @ 1-MHz offset, and the measured reference spur for LORF is less than -49 dBc. Thus, the extrapolated PN performance is better than -84 dBc/Hz @ 1 MHz at 70-78 GHz LORF. The embedded frequency synthesizer occupies 0.16-mm2 chip area, including the angular rotator and buffers, and consumes 65 mW under 1-V supply.

A 100–117 GHz W-Band CMOS Power Amplifier With On-Chip Adaptive Biasing

A low phase noise, wideband, mm-wave, integer-N PLL that is capable of supporting a 802.15.3c heterodyne TRX is reported. The PLL can generate 6 equally spaced tones from 43.2GHz to 51.84GHz, which is suitable for a heterodyne architecture with LO=(4/5)RF. Phase noise is measured directly at the LO frequency and is better than −97.5dBc/Hz@1MHz across the entire band. The total power consumption is 72mW from a 1V supply. The reported frequency synthesizer is smaller, exhibits less phase noise, and consumes less power than prior art. In addition, the LO tone corresponds to the fundamental of the VCO as opposed to a higher harmonic. Central to the PLL performance is the design of a low-noise, mm-wave VCO with a 22.9% tuning range. It is noted that resonator nonlinearities may result in significant up-conversion of flicker noise in wideband, mm-wave VCOs. To overcome this, Digitally-Controlled-Artificial-Dielectric (DiCAD) is used to linearize the resonator.

A

A self-healing two-stage 60 GHz power amplifier (PA) with amplitude/phase compensation is realized in 65 nm CMOS. An adaptive feedback bias scheme with three control knobs is proposed to extend the linear operating region and enhance chip-to-chip performance yield; allowing a 5.5 dB improvement of the output 1-dB compression point (P1dB) and a less than 2% chip-to-chip gain variation. At a 1 V supply, the fully differential PA achieves a saturation output power (Psat) of 14.85 dBm with a peak power-added-efficiency (PAE) of 16.2%. With the on-chip amplitude compensation, the P1dB is extended to 13.7 dBm. With the on-chip phase compensation, the output phase variation is minimized to less than 0.5 degree. To the best of our knowledge, this PA provides the highest Psat and P1dB with simultaneous high PAE for a single PA reported to date. The PA delivers a linear gain of 9.7 dB and has a 7 GHz bandwidth from 55.5 to 62.5 GHz with a very compact area of 0.042 mm2.

{\hbox{70}}{\hbox{–}} {\hbox{78-}}{\hbox{GHz}}

A fully differential 144GHz CMOS amplifier has been demonstrated in 65nm CMOS. It validates a maximum 20dB power gain and has positive gain over 38GHz frequency range from 126GHz to 164GHz. With stacking circuit architecture, the amplifier can tolerate up to 2V supply without reliability concern. It also delivers over 5.7dBm saturated output power with PldB of 5dBm under a 2V supply. The amplifier features a 3-stage common-source cascode architecture with on-chip interstage matching. The chip occupies 0.05 mm2 area and draws 39mA and 51mA from 1.4V and 2V supplies respectively. To our best knowledge, this amplifier achieves the highest power gain for CMOS amplifier beyond 100GHz and paves the way for D-band radar and passive imaging system applications.