Shilpi Birla

Static Noise Margin Analysis of Various SRAM Topologies

the present time, great emphasis has been given to the design of low-power and high performance memory circuits. As an SRAM is a critical component in both high-performance processors and hand-held portable devices. So the ever-increasing levels of on-chip integration of SRAM, offers serious design challenges in terms of power requirement and cell stability. There is a significant increase in the sub-threshold leakage due to its exponential relation to the threshold voltage, and gate leakage due to the reducing gate-oxide thickness. In order to minimize the leakage current, the supply voltage is reduced drastically which reduces the threshold voltage of the cell.This reduces the threshold voltage of the cell which results in reduction of the Static Noise Margin (SNM) of the cell and affect the data stability of the cell, seriously. In this work, the solutions for theses two problems, in the conventional 6T SRAM Cell has been explored.

Analysis of the Effects of the Operating Temperature at the Performance and Leakage Power Consumption in a Conventional CMOS 6T-SRAM Bit-Cell at 65nm, 45nm, and 32nm Technologies

—For mobile and multimedia applications of SRAMs, there is a strong need to reduce standby current leakages while keeping the memory cell data unchanged. To meet this objective, various techniques have been developed to reduce the leakage current at the process/device, circuit, architecture, and algorithmic levels. The traditional 6T CMOS SRAMs face many challenges in deep-submicron (DSM) technologies for low supply voltage (VDD) operation. Predictions suggests that process variations will limit standard 90nm SRAMs to around 0.7V operation because of the Static Noise Margin (SNM) degradation and write margin, also a VDD of 0.7V is reported for a 65nm SRAM. This work discusses some of the schemes that minimizes the cell leakage regardless of the process fluctuations and the environmental conditions. Various SRAM leakage currents identifies the suitable schemes for 6T SRAM sub-threshold operation at device and circuit levels for optimal sub-threshold circuit designs and provides an effective roadmap for digital circuit designers who are interested to work with ultra-low-power applications in CMOS technology.

Speed and Leakage Power Trade-off in Various SRAM Circuits

The growing demand of multimedia rich applications in handled portable devices continuously driving the need for large and high speed embedded Static Random Access Memory (SRAM) to enhance the system performance. Many circuit techniques, e.g. body bias, bit charge recycling etc., have been proposed to expand design margins at low voltage operation while reducing leakage current at standby mode, but the performance is analyzed at the cost of speed and this issue is not addressed widely. Also due to continuous scaling of CMOS, the process variations also affect the performance of SRAMs. This paper presents the analysis of low leakage SRAM along with the speed factor.

Leakage Current Reduction in 6T Single Cell SRAM at 90nm Technology

The emerging Wireless Sensor Network technologies are facilitating novel applications in health monitoring, industrial monitoring and security surveillance. The small physical dimensions of wireless sensor nodes often restrict the energy source to a small battery. The limited energy consumption requirement demands for ultra-low power sensing, processing and communication. This paper targets the modeling and simulation of CMOS leakage currents and its minimization approach to reduce the power consumption by a single cell SRAM cache. The popular approaches for leakage reduction are the data retention gated ground, and dynamic threshold voltage for cache. The work focuses on the simulation of a SRAM Cell for the data retention gated ground and drowsy mode SRAM Cell which shows that the current reduction of around 25% in s simulation model, respectively in comparison with the conventional cell with no current reduction technique.

Analysis of 8T SRAM Cell at Various Process Corners at 65 nm Process Technology

In Present scenario battery-powered hand-held multimedia systems become popular. The power consumption in these devices is a major concern these days for its long operational life. Although various techniques to reduce the power dissipation has been developed. The most adopted method is to lower the supply voltage. But lowering the Vdd reduces the gate current much more rapidly than the sub-threshold current and degrades the SNM. This degraded SNM further limits the voltage scaling. To improve the stability of the SRAM cell topology of the conventional 6T Static Random Access Memory (SRAM) cell has been changed and revised to 8T and 10T cell, the topologies. This work has analyzed the SRAM’s Static Noise Margin (SNM) at 8T for various process corners at 65nm technology. It evaluates the SNM along with the write margins of the cell along with the cell size of 8T SRAM bit-cell operating in sub-threshold voltage at various process corners. It is observed that an 8T cell has 13 % better write margin than conventional 6T SRAM cell. This paper analyses the dependence of SNM of SRAM memory cell on supply voltage, temperature, transistor sizing in 65nm technology at various process corners (TT, SS, FF, FS, and SF).

Characterization of 9T SRAM Cell at Various Process Corners at Deep Sub-micron Technology for Multimedia Applications

In the past decades CMOS IC technologies have been constantly scaled down and at present they aggressively entered in the nanometer regime. Amongst the wide-ranging variety of circuit applications, integrated memories especially the SRAM cell layout has been significantly reduced. As it is very well know the reduction of size of CMOS involves an increase in physical parameters variation, this is a factor which has a direct impact on SRAM cell stability. Polysilicon and diffusion critical dimensions (CD) together with implant variations are the main causes of mismatch in SRAM cells. SRAM memory cells have always been designed to occupy the minimum amount of silicon area consistent with the performance and reliability required. Todays system on Chip (SoC) trends result in a major percentage of the total die area being dedicated to memory blocks, consequently making SRAM parameter variations dominate the overall circuit parameter characteristics, including leakage, process variation effects, etc. The reliability is usually measured by static noise margin, SNM (1), and write trip point simulations and measurements. In this paper we have analyzed the stability of the 9T SRAM cell at SS, FF, TT, FS, SF corners. The simulations have been done at 45nm technology.

Stability and Leakage Analysis of a Novel PP Based 9T SRAM Cell Using N Curve at Deep Submicron Technology for Multimedia Applications

Due to continuous scaling of CMOS, stability is a prime concerned for CMOS SRAM memory cells. As scaling will increase the packing density but at the same time it is affecting the stability which leads to write failures and read disturbs of the conventional 6T SRAM cell. To increase the stability of the cell various SRAM cell topologies has been introduced, 8T SRAM is one of them but it has its limitation like read disturbance. In this paper we have analyzed a novel PP based 9T SRAM at 45 nm technology. Cell which has 33% increased SVNM (Static Voltage Noise Margin) from 6T and also 22%.reduced leakage power. N curve analysis has been done to find the various stability factors. As compared to the 10T SRAM cell it is more area efficient.

Leakage Current Minimization in Deep-Submicron Conventional Single Cell SRAM

The growing demand in the multimedia rich applications are motivating the low-power and high-speed circuit designer to work more closely towards the design issues arising from the design trade-offs in power and speed. This paper targets the modeling and simulation of CMOS leakage currents and its minimization approach to reduce the power consumption by a single cell SRAM cache. The popular approaches for leakage reduction are the data retention gated ground, a drowsy mode, and dynamic threshold voltage for cache. The work focuses on the simulation of a SRAM Cell for the data retention gated ground and drowsy mode SRAM Cell which shows that the current reduction of around 20% in first and 25% in second simulation model, respectively in comparison with the conventional cell with no current reduction technique.

Analysis of the Effect of Temperature and V dd on Leakage Current in Conventional 6T-SRAM Bit-Cell at 90nm and 65nm Technology

The increased demand for battery operated portable semiconductor applications and continuous scaling of CMOS devices, results high packaging density but increases the importance of power even more noticeable for a new class of energy constrained systems. Recent Low-Power VLSI design interest is in operating the CMOS circuits with power supply voltage below the transistor threshold operation. As subthreshold circuits can allow ultra-low power designs to be fabricated on modern CMOS process technology, sub-threshold operation is applicable to wide range of applications ranging from wireless devices, biomedical applications, spacecraft related applications, etc. Lowering the supply voltage to reduce power consumption is one of the choices of the designers for designing low power SRAM circuits. For mobile/multimedia applications of SRAMs, there is a need to reduce standby leakage current while keeping memory cell data. In technology beyond 130nm low-power SRAM is severely complicated by intra die-variations and leakage power. For SRAM cells, leakage reduction has been obtained with low supply voltages and high threshold (HVT) transistors. In this work we have simulated a conventional 6T SRAM cell and analyzed the effect of the leakage and standby currents of 6T cell with respect to various supply voltage (Vdd) and operating temperatures at deep sub-micron technologies, i.e., 90nm and 65nm CMOS process. Here, the effect of temperature is observed on leakage currents at different supply voltages. As the temperature increases for 40C to 100C, it is observed that the leakage goes upto 90% in 90nm and 89% in 65nm at Vdd of 1V and 0.5V, respectively.

New Modeling Technology for Spiral Inductors for Ultra Wideband Applications

Spiral Inductor is becoming a crucial element for the increasing demands of the emerging wireless communication designs. Yet, the challenges of modeling spiral inductors for narrow-band applications are increasing along with emerging Ultra-Wideband (UWB) wireless applications. The challenge is to get an accurate model for UWB applications. A characterization using simulation offers more flexibility during the design process of the spirals. This approach also avoids the need for a specific test wafer dedicated to the spirals, a process parameter characterization suffices. As simulation adds predictive nature in the design process, changes can be made more easily to optimize and fine-tune the layout of the spiral for an optimal inductance value and quality factor. This optimization process can even be automated. Parameter studies can reveal sensitivities and insight on how to improve the behavior of the spiral. A simulation-based approach requires an accurate, computationally efficient and user-friendly tool. This paper discusses integrated spiral inductor metrics, key physical design challenges, and current modeling approaches and limitations. It introduced a new EM solver for introduces a new spiral inductor modeling methodology and application example that is well suited to UWB wireless applications.