Manisha Pattanaik

Clock Gating Aware Low Power ALU Design and Implementation on FPGA

This paper deals with the design and implementation of a Clock Gating Aware Low Power Arithmetic and Logic Unit that has been developed as part of low power processor design in the platform Xilinx ISE 14.2 and synthesized on 90nm Spartan-3 FPGA. Clock power contributes 45-60 percent of total dynamic power. Hence, clock power reduction is necessary in low power design. In this paper, we analyze theoretical 93.75% clock power reduction in ALU using clock gating techniques. On simulator, we achieved 88.23% clock power reduction using latch based clock gating and 70.58% clock power reduction using latch free clock gating. Index Terms—Clock gate, ALU, FPGA, LUT, clock power, register transfer level, dynamic power, leakage power

Clock gated low power sequential circuit design

In this work, our focus is on study and analysis of various clock gating technique and design and analysis of clock gating based low power sequential circuit at RTL level. Virtex-6 is 40-nm FPGA, on which we implement our circuit to re-assure power reduction in sequential circuit. Clock gating is implemented on smaller circuit called D flip-flop and on larger circuit called 16-bit register. The percentage of reduction in dynamic power especially clock power is verified for different device operating frequency. Here, we achieved 87.09%, 88.02%, 88.02%, and 88.01% clock power reduction in this work when clock period is 1ns, 0.1ns, 0.01ns and 0.001ns respectively. Design and implementation result shows that there is reduction in dynamic power especialy significant reduction in clock power We also achieved 15%, 14.22%, 14.58%, 14.57% and 14.57% dynamic power reduction when clock period is 10ns, 1ns, 0.1ns, 0.01ns, and 01ps respectively.

Clock gating based energy efficient ALU design and implementation on FPGA

In this paper, latch free clock gating techniques is applied in ALU to reduce clock power and dynamic power consumption of ALU. Clock power is 50%, 41.46%, 51.30%, 55.15% and 55.78% of total dynamic power when device operating frequency is 100MHz, 1GHz, 10GHz, 100GHz and 1 THz. After implementation of clock gating techniques in ALU, Clock power reduces to 17.85%, 23.39%, 26.49% and 27.19% of total dynamic power, when device operating frequency is 1GHz, 10GHz, 100GHz and 1 THz. On 1 THz operating frequency, when we use clock gating, there are 72.77% reduction in clock power, 38.88% reduction in IOs power and 44% reduction in dynamic power in compare to power consumption without using clock gating techniques. Target device is 90-nm Spartan-3. There is 14.57% reduction in junction temperature on 10GHz operating frequency in compare to temperature without using clock gating techniques. Clock gating saves power but increases over all area. There is 32.35%, 37.84%, 43.31% and 44% reduction in dynamic current when we use clock gate on 1GHz, 10GHz, 100GHz and 1THz operating frequency respectively.

Histogram statistics based variance controlled adaptive threshold in anisotropic diffusion for low contrast image enhancement

It is very difficult in low contrast images to distinguish between the noisy background and the regions of low gray level inter-region edges. The classical Perona-Malik anisotropic diffusion is able to smooth the defective background but cannot enhance faultless low gray level inter-region edges in such low contrast images. The proposed method provides an unsupervised machine learning process to modify the anisotropic diffusion by generating an adaptive threshold in diffusion coefficient function using statistical measures. In the proposed method, image histogram is employed to calculate the global gray level variance over the entire image and local gray level variance over the defined neighborhood of each pixel of given image. The adaptive threshold in diffusion coefficient function varies in accordance with the difference between the two variances which gives a measure of intensity contrast in that neighborhood. The experimental results from various low contrast images have shown that the proposed unsupervised machine learning approach for adaptive threshold selection in anisotropic diffusion can effectively smooth noisy background with preservation of low gradient edges.

Design and Analysis of a Novel Low-Power SRAM Bit-Cell Structure at Deep-Sub-Micron CMOS Technology for Mobile Multimedia Applications

The growing demand for high density VLSI circuits and the exponential dependency of the leakage current on the oxide thickness is becoming a major challenge in deep-sub-micron CMOS technology. In this work, a novel Static Random Access Memory (SRAM) Cell is proposed targeting to reduce the overall power requirements, i.e., dynamic and standby power in the existing dual-bit-line architecture. The active power is reduced by reducing the supply voltage when the memory is functional and the standby power is reduced by reducing the gate and sub-threshold leakage currents when the memory is idle. This paper explored an integrated approach at the architecture and circuit level to reduce the leakage power dissipation while maintaining high performance in deep-submicron cache memories. The proposed memory bit-cell makes use of the pMOS pass transistors to lower the gate leakage currents while full-supply body-biasing scheme is used to reduce the sub-threshold leakage currents. To further reduce the leakage current, the stacking effect is used by switching off the stack transistors when the memory is ideal. In comparison to the conventional 6T SRAM bit-cell, the total leakage power is reduced by 50% while the cell is storing data ‘1’ and 46% when data ‘0’ at a very small area penalty. The total active power reduction is achieved by 89% when cell is storing data 0 or 1. The design simulation work was performed on the deep-sub-micron CMOS technology, the 45nm, at 250C with VDD of 0.7V.

Low Power VLSI Circuit Design with Efficient HDL Coding

In this paper, four-bit unsigned up counter with an asynchronous clear and a clock enable is designed in Xilinx ISE 14.2 and implemented on high performance Virtex-6 FPGA, XC6VLX240T device, -1 speed grade, FFG1156 package and ML605 board. User constraints file (ucf) and net list constraints design (ncd) file are taken into consideration with XPower 14.2 for power consumption analysis. We take two codes. Our first code maps the clock enable signal to LUTs then the power consumption is 3.423 Watt. Our second code maps the clock enable signal to control ports then the power consumption is 3.625 Watt. By changing mapping style, we reduce 6% power reduction and also reduce number of LUT and D flip-flop used in implementation leads to area efficient design. By efficiently mapping, we reduce power consumption in multiple of power reduction with single statements. The experimental result shows the power analysis of both HDL mapping code.

Analysis of the Effects of the Operating Temperature at the Performance and Leakage Power Consumption in a Conventional CMOS 6T-SRAM Bit-Cell at 65nm, 45nm, and 32nm Technologies

—For mobile and multimedia applications of SRAMs, there is a strong need to reduce standby current leakages while keeping the memory cell data unchanged. To meet this objective, various techniques have been developed to reduce the leakage current at the process/device, circuit, architecture, and algorithmic levels. The traditional 6T CMOS SRAMs face many challenges in deep-submicron (DSM) technologies for low supply voltage (VDD) operation. Predictions suggests that process variations will limit standard 90nm SRAMs to around 0.7V operation because of the Static Noise Margin (SNM) degradation and write margin, also a VDD of 0.7V is reported for a 65nm SRAM. This work discusses some of the schemes that minimizes the cell leakage regardless of the process fluctuations and the environmental conditions. Various SRAM leakage currents identifies the suitable schemes for 6T SRAM sub-threshold operation at device and circuit levels for optimal sub-threshold circuit designs and provides an effective roadmap for digital circuit designers who are interested to work with ultra-low-power applications in CMOS technology.

Analysis and reduction of ground bounce noise and leakage current during mode transition of stacking power gating logic circuits

Power gating is an effective method to reduce leakage current in logic circuits during sleep mode. However, conventional power gating technique for minimizing leakage current introduces ground bounce noise during sleep to active mode transition. In this paper, a high performance stacking power gating structure is introduced which minimizes the leakage power and provides a way to control the ground bounce noise in transition mode. Stacking power gating technique has been analyzed and the conditions for the important design goals such as (i) Minimum ground bounce noise and (ii) Minimum wakeup latency have been derived. The tradeoff between the ground bounce noise and wakeup latency has been explored for high performance power gating logic circuits. Further, to evaluate the efficacy of the proposed stacking power gating technique, simulation has been done using proposed technique and implemented on basic 2-input NAND gate circuit with BPTM 90nm technology. The leakage current is reduced by 81.1% over the conventional power gating technique. Ground bounce noise has also been reduced to 76.28% as comparison to the conventional power gating technique.

Performance Analysis of 90nm Look Up Table (LUT) for Low Power Application

This paper provides a detailed performance analysis of low power and high speed Look up Table (LUT) by using a circuit technique. Proper sizing of all the sleep transistors are done in the LUT to achieve an optimum power –delay relationship so that it can be used for fast growing low power applications. Also, we have implemented a benchmark circuit (8 × 10) encoder in Virtex-4, 90nm FPGA. As compared to the traditional 4-input LUT design, proposed design saves 12.8% of average power in high speed mode and 56.7% in low power mode with a little compromise in its speed.

SmartCQL: Semantics to Handle Complex Queries over Data Streams

SmartCQL, enhanced version of CQL is developed so as to provide semantics to handle complex queries. Simple SPJ (Select Project Join) queries are no longer useful and the existing CQL supports complex queries only to a certain extent. But the main goal of SmartCQL is to enhance this feature to a large extent. We achieved this goal by providing semantics to handle complex queries like sub queries which was not handled by CQL. We solved the famous Linear Road problem, benchmark for data streams with minimum number of queries as compared to CQL. Here we will show how SmartCQL increased the expressiveness to a greater extent.