Shin'ichi Wakabayashi

A systolic regular expression pattern matching engine and its application to network intrusion detection

This paper proposes a high-speed string matching circuit for searching a pattern in a given text. In the circuit, a pattern is specified by a class of restricted regular expressions. The architecture of the proposed circuit is a one-dimensional systolic architecture consisting of simple processing units. It can be effectively used for network intrusion detection systems (NIDSs).

Faster algorithms for finding a minimum K-way cut in a weighted graph

This paper presents algorithms for computing a minimum 3-way cut and a minimum 4-way cut of an undirected weighted graph G. Let G=(V,E) be an undirected graph with n vertices, m edges and positive edge weights. Goldschmidt et al. presented an algorithm for the minimum /spl kappa/-way cut problem with fixed /spl kappa/, that requires O(n/sup 4/) and O(n/sup 9/) maximum flow computations, respectively, to compute a minimum 3-way cut and a minimum 4-way cut of G. In this paper, we first show some properties on minimum 3-way cuts and minimum 4-way cuts, which indicate a recursive structure of the minimum X-way cut problem when /spl kappa/=3 and 4. Then, based on those properties, we give divide-and-conquer algorithms for computing a minimum 3-way cut and a minimum 4-way cut of G, which require O(n/sup 3/) and O(n/sup 4/) maximum flow computations, respectively. This means that the proposed algorithms are the fastest ones ever known.

An FPGA-based text search engine for approximate regular expression matching

Text search is a procedure to find occurrences of a pattern in a given text where the pattern and each occurrence may have a limited number of differences. Text search is an indispensable technique for bibliographic databases. In this paper, a restricted class of regular expressions is used as patterns, and all substrings in a text that are close to a pattern, possibly with some errors, are located. We call this text search problem approximate regular expression matching. For this problem, a one-dimensional systolic algorithm is presented based on dynamic programming. Experiments show that the proposed hardware engine implemented on FPGA realizes high-speed text search.

Pin assignment with global routing for VLSI building block layout

In this paper, we will consider global routing and pin assignment in VLSI building block layout, and present an efficient algorithm which integrates global routing, pin assignment, block reshaping and positioning. The general flow of the proposed algorithm is the same as the one proposed in by Cong in 1991 [1] and consists of two main phases. The first phase is to determine not only global routes and coarse pin assignment in the same way as [1], but also shapes and positions of blocks. The second phase is to compute the final pin assignment for channels. We generalize the channel pin assignment (CPA) problem in [1], in which the CPA problem is formulated for only channels formed by two blocks, to the CPA problem for channels formed by multiple blocks. We will propose a linear time optimal channel pin assignment algorithm, which is an extension of the algorithm in [1]. Experimental results show the effectiveness of the proposed algorithm.

FPGA implementation of tabu search for the quadratic assignment problem

In this paper, we propose an FPGA implementation of tabu search to solve the quadratic assignment problem in a short execution time. In the proposed hardware implementation of tabu search, multiple neighbor solutions are evaluated in parallel and each solution is evaluated in a pipeline fashion. The proposed method effectively utilizes internal block RAMs of recent large scale FPGAs. Experimental results show the efficiency and effectiveness of the proposed method

A timing-driven global routing algorithm with pin assignment, block reshaping, and positioning for building block layout

This paper presents a timing-driven global routing algorithm based on coarse pin assignment, block reshaping, and positioning for VLSI building block layout. As opposed to conventional approaches, we combine pin assignment and global routing problems into one problem. The proposed algorithm determines global routes, coarse pin assignments, and block shape and positions so as to minimize the chip area and total wire length of nets under the given timing constraints. It is based on an iterative improvement paradigm and performs rip-up and rerouting, block reshaping, and positioning in the manner of simulated evolution taking shapes of soft blocks and routing congestion into consideration until the solution is not improved. The Elmore delay model is adopted for the interconnection delay model. Experimental results show the effectiveness of the proposed algorithm.

An Instance-Specific Hardware Algorithm for Finding a Maximum Clique

This paper presents a hardware algorithm for finding a maximum clique of a given graph, and shows experimental results of the proposed algorithm running on an FPGA. The proposed algorithm is constructed according to a given instance of graph, and can find a maximum clique efficiently based on branch and bound search. The proposed algorithm is designed to be implemented on FPGAs, and realizes an efficient branch and bound search with parallel and pipeline processing. Experimental results showed that, compared with the software solver, the proposed algorithm produced a maximum clique in a very shorter running time even if the time for circuit synthesis and configuration of FPGA was taken into account.

A timing-driven global routing algorithm considering channel density minimization for standard cell layout

This paper presents a new timing-driven global routing method for standard cell layout. The proposed method can explicitly consider the timing constraint between two registers and minimize the channel density under the given timing constraint. First, we determine the initial global routes. Next, we improve the global routes to satisfy the timing constraint between two registers as well as to minimize the channel density. Finally, for each cell row, the nets incident to terminals an the cell row are assigned to channels to minimize the channel density using 0-1 integer linear programming. We also show experimental results of the proposed method implemented on an engineering workstation, which show that the proposed method is quite promising.

A Multithreaded Parallel Global Routing Method with Overlapped Routing Regions

Routing is one of the time-consuming processes in LSI design to connect previously placed terminals. In this study, we propose a multithreaded parallel routing algorithm for LSI design. In the proposed method, first, threads are created and the nets of the target net list are equally distributed to the threads. Sharing the routing regions, each of the threads searches a candidate path of a net in parallel without synchronization. Then, each thread exclusively writes a candidate path to the routing regions as a determined path. Although the exclusive control is necessary when updating the routing regions, this asynchronous parallel routing reduces the wait time of the threads. If a candidate path of a net does not satisfy constraints due to the asynchronous parallel routing, the net is re-routed. We experimentally confirmed that our proposed method running on a PC with eight cores was 7.1 times faster than the sequential execution. In addition, we also confirmed that the routing quality was not degraded compared to the sequential execution.

An Efficient Hardware Matching Engine for Regular Expression with Nested Kleene Operators

In this paper, we propose a systolic pattern-independent hardware regular expression matching (REM) engine which handles nested Kleene operators used in virus patterns. Pattern-independent systolic REM engines are suitable to network intrusion detection systems for quick updating of virus pattern. In the proposed engine, we introduce a compact pattern-independent NFA circuit, which can handle any small regular expression patterns, into a systolic REM engine to handle nested Kleene operators. Experimental results show that the extended engine implemented on an FPGA handles nested Kleene operators with efficient circuit size and high performance (2.17Gbps).