Shinobu Nagayama

Numerical Function Generators Using LUT Cascades

This paper proposes an architecture and a synthesis method for high-speed computation of fixed-point numerical functions such as trigonometric, logarithmic, sigmoidal, square root, and combinations of these functions. Our architecture is based on the lookup table (LUT) cascade, which results in a significant reduction in circuit complexity compared to traditional approaches. This is suitable for automatic synthesis and we show a synthesis method that converts a Matlab-like specification into an LUT cascade design. Experimental results show the efficiency of our approach as implemented on a field-programmable gate array (FPGA)

Complexities of Graph-Based Representations for Elementary Functions

This paper analyzes complexities of decision diagrams for elementary functions such as polynomial, trigonometric, logarithmic, square root, and reciprocal functions. These real functions are converted into integer-valued functions by using fixed-point representation. This paper presents the numbers of nodes in decision diagrams representing the integer-valued functions. First, complexities of decision diagrams for polynomial functions are analyzed, since elementary functions can be approximated by polynomial functions. A theoretical analysis shows that binary moment diagrams (BMDs) have low complexity for polynomial functions. Second, this paper analyzes complexity of edge-valued binary decision diagrams (EVBDDs) for monotone functions, since many common elementary functions are monotone. It introduces a new class of integer functions, Mp-monotone increasing function, and derives an upper bound on the number of nodes in an EVBDD for the Mp-monotone increasing function. A theoretical analysis shows that EVBDDs have low complexity for Mp-monotone increasing functions. This paper also presents the exact number of nodes in the smallest EVBDD for the n-bit multiplier function, and a variable order for the smallest EVBDD.

Representations of Elementary Functions Using Binary Moment Diagrams

This paper considers representations for elementary functions such as polynomial, trigonometric, logarithmic, square root, and reciprocal functions. These real valued functions are converted into integer functions by using fixed-point representation, and they are represented by using binary moment diagrams (BMDs). Elementary functions are represented compactly by applying the arithmetic transform to the functions. For polynomial functions, upper bounds on the numbers of nodes in BMDs and multiterminal binary decision diagrams (MTBDDs) are derived. These results show that for polynomial functions, BMDs require fewer nodes than MTBDDs. Experimental result for 16-bit precision sin(x) function shows that the BMD requires only 20% of the nodes for the MTBDD.

Analysis of Multi-state Systems with Multi-state Components Using EVMDDs

This paper proposes a new analysis method of multi-state systems with multi-state components using multi-valued decision diagrams (MDDs). The multi-state systems with multi-state components can be considered as multi-valued functions, called structure functions. Since the structure functions are usually monotone increasing functions, they can be represented compactly using edge-valued MDDs (EVMDDs). This paper proposes an efficient analysis method using EVMDDs. It shows that by using EVMDDs, the structure functions can be represented more compactly than existing methods using ordinary MDDs, and systems can be analyzed with comparable computation time.

Representations of Elementary Functions Using Edge-Valued MDDs

This paper proposes a method to represent elementary functions such as trigonometric, logarithmic, square root, and reciprocal functions using edge-valued multi-valued decision diagrams (EVMDDs). We introduce a new class of integer functions, Mp-monotone increasing functions, and derive an upper bound on the number of nodes in an edge-valued binary decision diagram (EVBDD) for the Mp-monotone increasing function. The upper bound shows that EVBDDs represent Mp-monotone increasing functions more compactly than other decision diagrams when p is small. Experimental results using 16-bit precision elementary functions show that: 1) standard elementary functions can be converted into Mp-monotone increasing functions with p = 1 or p = 2, or their linear transformations. And, they can be compactly represented by EVBDDs. 2) EVMDDs represent elementary functions with, on average, only 11% of the memory size needed for binary moment diagrams (BMDs), and only 69% of the memory size needed for EVBDDs.

Programmable numerical function generators: architectures and synthesis method

This paper presents an architecture and a synthesis method for programmable numerical function generators of trigonometric functions, logarithm functions, square root, reciprocal, etc. Our architecture uses an LUT (look-up table) cascade as the segment index encoder, compactly realizes various numerical functions, and is suitable for automatic synthesis. We have developed a synthesis system that converts MATLAB-like specification into HDL code. We propose and compare three architectures implemented as a FPGA (field-programmable gate array). Experimental results show the efficiency of our architecture and synthesis system.

Design Method for Numerical Function Generators Based on Polynomial Approximation for FPGA Implementation

This paper focuses on numerical function generators (NFGs) based on k-th order polynomial approximations. We show that increasing the polynomial order k reduces significantly the NFGs memory size. However, larger k requires more logic elements and multipliers. To quantify this tradeoff, we introduce the FPGA utilization measure, and then determine the optimum polynomial order k. Experimental results show that: 1) for low accuracies (up to 17 bits), 1st order polynomial approximations produce the most efficient implementations; and 2) for higher accuracies (18 to 24 bits), 2nd-order polynomial approximations produce the most efficient implementations.

Compact Numerical Function Generators Based on Quadratic Approximation: Architecture and Synthesis Method*This paper is an extension of [15].

This paper presents an architecture and a synthesis method for compact numerical function generators (NFGs) for trigonometric, logarithmic, square root, reciprocal, and combinations of these functions. Our NFG partitions a given domain of the function into non-uniform segments using an LUT cascade, and approximates the given function by a quadratic polynomial for each segment. Thus, we can implement fast and compact NFGs for a wide range of functions. Experimental results show that: 1) our NFGs require, on average, only 4% of the memory needed by NFGs based on the linear approximation with non-uniform segmentation; 2) our NFG for 2x-1 requires only 22% of the memory needed by the NFG based on a 5th-order approximation with uniform segmentation; and 3) our NFGs achieve about 70% of the throughput of the existing table-based NFGs using only a few percent of the memory. Thus, our NFGs can be implemented with more compact FPGAs than needed for the existing NFGs. Our automatic synthesis system generates such compact NFGs quickly.

Design Method for Numerical Function Generators Using Recursive Segmentation and EVBDDs

Numerical function generators (NFGs) realize arithmetic functions, such as ex, sin(πx), and √x, in hardware. They are used in applications where high-speed is essential, such as in digital signal or graphics applications. We introduce the edge-valued binary decision diagram (EVBDD) as a means of reducing the delay and memory requirements in NFGs. We also introduce a recursive segmentation algorithm, which divides the domain of the function to be realized into segments, where the given function is realized as a polynomial. This design reduces the size of the multiplier needed and thus reduces delay. It is also shown that an adder can be replaced by a set of 2-input AND gates, further reducing delay. We compare our results to NFGs designed with multi-terminal BDDs (MTBDDs). We show that EVBDDs yield a design that has, on the average, only 39% of the memory and 58% of the delay of NFGs designed using MTBDDs.

Programmable Architectures and Design Methods for Two-Variable Numeric Function Generators

This paper proposes programmable architectures and design methods for numeric function generators (NFGs) of two-variable functions. To realize a two-variable function in hardware, we partition a given domain of the function into segments, and approximate the function by a polynomial in each segment. This paper introduces two planar segmentation algorithms that efficiently partition a domain of a two-variable function. This paper also introduces a design method for symmetric two-variable functions (i.e. f(X, Y)=f(Y, X)). This method can reduce the memory size needed for symmetric functions by nearly half with small speed penalty. The proposed architectures allow a systematic design of various two-variable functions. We compare our approach with one based on a one-variable NFG. FPGA implementation results show that, for a complicated function, our NFG achieves 57% of memory size and 60% of delay time of a circuit designed based on a one-variable NFG.