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Dive into the research topics where Shin-ichiro Hayano is active.

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Featured researches published by Shin-ichiro Hayano.


IEEE Journal of Solid-state Circuits | 1993

A Si bipolar 1.4-GHz time space switch LSI for B-ISDN

Osamu Matsuda; Shin-ichiro Hayano; Takao Takeuchi; Hideki Kitahata; Hisashi Takemura; Tsutomu Tashiro

A 155-MB/s 32*32 Si bipolar switch LSI designed for wide application in the broadband ISDN was implemented. The operating speed is 1.4 GHz using an A-BSA Si bipolar process. Its throughput is 5.0 Gb/s by handling four 1.4-GHz interfaces, each of which supports an eight-channel multiplexed data stream. To realize a highly integrated high-speed bipolar LSI, power consumption and chip area should be reduced. Two technologies were developed for the LSI: (1) an active pull-down circuit with an embedded bias circuit in each gate, and (2) a modified standard cell with overlapped cell-channel structure. Using these technologies, total power consumption and chip area were reduced to 60% and 70%, respectively, of what is expected when conventional emitter-coupled logic (ECL) technologies and standard cell structures are used. The LSI evaluation results show that the developed LSI has sufficient performance to realize a large-scale B-ISDN switching system. >


symposium on vlsi circuits | 1992

A Si bipolar 1.4 GHz time space switch LSI for B-ISDN

Osamu Matsuda; Shin-ichiro Hayano; Takao Takeuchi; Hideki Kitahata; Hisashi Takemura; Tsutomu Tashiro

The advanced active pull-down circuitry and the layout design technique to realize a high-speed, low-power LSI have been developed. A 32-channel broadband switch LSI operating at a 1.4-GHz clock-rate has been built to serve as a key component for B-ISDN systems. The total chip power dissipation is reduced by 60% compared with conventional ECL chips while avoiding the effect of cross talk noise. The chip area is reduced by 70% compared with a common standard cell structure.<<ETX>>


Archive | 1990

Call control with transmission priority in a packet communication network of an atm type

Shin-ichiro Hayano; Hiroshi Suzuki


Archive | 1988

Time division switching for multi-channel calls using two time switch memories acting as a frame aligner

Shin-ichiro Hayano


Archive | 1989

Multiplexer/demultiplexer circuitry for LSI implementation

Shin-ichiro Hayano


Archive | 1988

Time-division multiplex switching network

Shin-ichiro Hayano


Archive | 2001

Method and system for notification of maintenance information using portable terminal and computer program product

Susumu Sasabe; Shin-ichiro Hayano; Toshibumi Kawano; Yasuhiro Uemura; Hiroyuki Hayashi; Shingo Fukui


IEEE Journal on Selected Areas in Communications | 1987

Synchronous Composite Packet Switching-A Switching Architecture for Broadband ISDN

Takao Takeuchi; Takehiko Yamaguchi; Hiroki Niwa; Hiroshi Suzuki; Shin-ichiro Hayano


Archive | 1990

Time division switching system with time slot alignment circuitry

Shin-ichiro Hayano


Archive | 1992

HIGH-SPEED CML PUSH-PULL LOGIC CIRCUIT HAVING TEMPERATURE COMPENSATED BIASING

Shin-ichiro Hayano; Osamu Matsuda

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