Shin-Il Lim

A 6-bit 2.704Gsps DAC for DS-CDMA UWB

This paper presents a design of a 6-bit 2.704Gsamples/s D/A converter (DAC) for DS-CDMA UWB transceivers. The proposed DAC was designed with a current steering segmented 4+2 architecture for high frequency sampling rate. For low glitches, optimized deglitch circuit is adopted for the selection of current sources. The measured integral nonlinearity (INL) is -0.081 LSB and the measured differential nonlinearity (DNL) is -0.065 LSB. The DAC implemented in a 0.13mum CMOS technology shows s spurious free dynamic range (SFDR) of 41dB at f signal 300Mhz. The prototype DAC consumes 28mW for a Nyquist sinusoidal output signal at a 2.704Gsamples/s. The chip has an active area of 0.76mm2

Design of a 6 bit 1.25 GS/s DAC for WPAN

This paper describes a 6 bit 1.25 GS/s DAC (digital-analog converter) for WPAN transceivers. The proposed DAC is designed with a current steering segmented 2+4 architecture to achieve low power consumption and a small die area. A master-slave deglitch circuit and regulated cascode current sources are proposed to improve the dynamic performance of the DAC. The DAC, implemented in a 0.18 um CMOS technology, shows a SFDR of 49.4 dB at the output signal of 551 MHz. The prototype DAC consumes 6 mW for a Nyquist sinusoidal output signal at a sampling rate of 1.25 GHz with the supply voltage of 1.8 V. The active area of the chip is 0.0576mm2.

A 4-bit 1.356 Gsps ADC for DS-CDMA UWB System

In this paper, a 4-bit 1.356GS/S analog to digital (A/D) converter targeted for the direct spectrum code division multiple access ultra wide band (DS-CDMA UWB) is presented. The A/D converter uses a fully differential flash architecture. To achieve low power consumption and high conversion rate, the proposed converter is designed with current mode amplifier (CMA) and each preamplifier includes a dual sense amplifier (DSA). The A/D converter can sample input frequencies above 650 MHz with this current mode processing technique. The A/D converter achieves 3.7 effective number of bits (ENOBs) for a 30MHz sinusoidal input and 3.35 ENOBs for a 650 MHz input at a 1.356 GHz sampling rate. At 1.356 GS/s, the current consumption is 38 mA including digital logic with a power supply of 1.8V. The proposed A/D converter is fabricated using a 0.18-mum 6Metal lPoly CMOS process and the active area is 0.35 mm2.

A 12-b Asynchronous SAR Type ADC for Bio Signal Detection

This paper describes a low power asynchronous successive approximation register (SAR) type 12b analog-to-digital converter (ADC) for biomedical applications in a 0.35 μm CMOS technology. The digital-to-analog converter (DAC) uses a capacitive split-arrays consisting of 6-b main array, an attenuation capacitor C and a 5-b sub array for low power consumption and small die area. Moreover, splitting the MSB capacitor into subcapacitors and an asynchronous SAR reduce power consumption. The measurement results show that the proposed ADC achieved the SNDR of 68.32 dB, the SFDR of 79 dB, and the ENOB (effective number of bits) of 11.05 bits. The measured INL and DNL were 1.9LSB and 1.5LSB, respectively. The power consumption including all the digital circuits is 6.7 μW at the sampling frequency of 100 KHz under 3.3 V supply voltage and the FoM (figure of merit) is 49 fJ/conversion-step.

Design of a 12-b asynchronous SAR CMOS ADC

A low power asynchronous SAR 12b ADC for biomedical applications was designed in a 0.35μm CMOS technology. The split capacitor array DAC with an asynchronous SAR was employed for low power consumption and small die area. Measurement results show that the proposed ADC achieved the SNDR of 68.32 dli, the SFDR of79dB, and the ENOB of11.05 bits. The measured INL and DNL were 1.9/−1.3 LSBs and 1.5/−0.9 LSBs, respectively. The power consumption including all the digital circuits and FOM were measured to be 6.8μW and 49 fJ/Step, respectively at the sampling frequency of 99 KHz.

An 8-bit 250MSPS CMOS pipelined ADC using open-loop architecture

This paper describes some design techniques for high speed and low power pipelined 8-bit 250MSPS ADC. To perform high-speed operation with relatively low power consumption, open loop architecture is adopted, while closed loop architecture (with MDAC) is used in conventional pipeline ADC. To reduce the power consumption and the die area, the number of amplifiers in each stage are optimized and reduced with proposed zero-crossing point generation method. At 250MHz sampling rate, measurement results show that the power consumption is 150mW including digital logic with 1.8V power supply. And the proposed ADC achieves 38dB (SNDR) with input frequency up to 125-MHz and input range of 1.2Vpp (Differential). The ADC is designed using a 0.18 /spl mu/m 6-Metal 1-Poly CMOS process and occupies an area of 900 /spl mu/m /spl times/ 500 /spl mu/m.

Biochemical sensor interface circuits with differential difference amplifier

A simple three-electrode CMOS interface system for electrochemical sensor is described. To maintain a constant potential between the reference electrode (RE) and working electrode (WE), only one differential difference amplifier (DDA) is exploited in this proposed design, while conventional sensor interface system requires at least 2 operational amplifiers and 2 resistors, or more than 3 operational amplifiers and 4 resistors for low voltage differential CMOS integrated interface circuits. The DDA with rail-to-rail design not only enables the full range operation to supply voltage but also provides simple interface system with small hardware and low power consumption. This new interface system was implemented in a 0.35um standard CMOS technology and experimentally verified.

A 10-bit 1.25GSample/s partially-segmented D/A Converter for Ultra Wide-Band communication system

This paper proposes a 10-bit 1.25GSample/s partially-segmented D/A converter for Ultra Wide-Band communication system fabricated in a digital 0.18um 1-poly 6-metal standard CMOS technology. To achieve low power consumption and small chip area with good linearity we employ partially segmented D/A converter architecture. Also, we use deglitch circuit and common-centroid layout scheme in the current cell matrix to obtain good linearity of the converter. Simulation results show that the implemented D/A converter has 73dB SFDR at 426MHz input signal with 49.5mW power consumption. The maximum integral nonlinearity (INL) is 0.3LSB and the maximum differential nonlinearity (DNL) is 0.15LSB. The active chip area is 2.21mm2.

A 6-bit 2.5GSample/s Flash ADC using Immanent C2MOS Comparator in 0.18um CMOS

The authors propose a 6-bit 2.5Gsample/s flash-ADC realized in a digital 0.18mum 1-poly 4-metal CMOS technology. To achieve low power with wide analog bandwidth and good performance, the authors employ active interpolation and new comparator latch scheme. The simulation results show that the implemented A/D converter has an effective number of bits (ENOB) of 5.99bit at 224MHz input while consuming 296mW and 5.86bit at 1240MHz input while consuming 341mW operating at 2.5GS/s clock frequency. This corresponds to figure-of-merit numbers (FoM) of 2.36 pJ/convstep at 1240MHz input. The total active area is 0.71mm2.

A chip design for body composition analyzer

This paper describes a chip design technique for body composition analyzer based on the BIA (bioelectrical impedance analysis) method. All the functions of signal forcing circuits to the body, signal detecting circuits from the body, Micom, SRAM and EEPROMs are integrated in one chip. Especially, multi-frequency detecting method can be applied with selective band pass filter (BPF), which is designed in weak inversion region for low power consumption. In addition, new full wave rectifier (FWR) is also proposed with differential difference amplifier (DDA) for high performance (small die area, low power consumption, rail-to-rail swing). The prototype chip was implemented with 0.35 mum CMOS technology and shows the power dissipation of 6 mW at the supply voltage of 3.3V. The die area of prototype chip is 5 mm times 5 mm.