Shing Tenqchen

XNOR-based double-edge-triggered flip-flop for two-phase pipelines

The conventional approach of double-edge-triggered flip-flops (DET-FFs) is to have two similar edge-triggered latches. And the achieved faster speed is at the cost of double chip area and complex logic structure. By contrast, the XNOR-based approaches is difficult to reach the speed demand due to the delay of the XNOR -based clock generator. This paper proposes a new designed DET-FF based on an alternative XNOR gate. By utilizing the sensitivity to the driving capacity of the previous stage, we use this simplified XNOR gate as a pulse-generator. A modified transparent latch following the pulse-generator acts as an XNOR-based DET-FF, which accomplishes the almost same speed and less power dissipation as compared with two conventional DET-FFs under HSPICE simulation. We also implemented the XNOR-based DET-FF in a two-phase-pipeline system, and the HSPICE simulation in the TSMC 0.25 um CMOS process shows our proposed DET-FF is much faster than those two conventional DET-FFs.

Design of a lower-error fixed-width multiplier for speech processing application

A lower-error and lower-variance n/spl times/n multiplier is suitably proposed for VLSI design. Considering the next lower significant stage in P/sub n-1/ column and a useful error-compensation model in the least significant part, and utilizing a near optimized index to classify the error terms are our strategies in order to achieve lower error and variance as compared with previously proposed structure in the subproduct-array of the Baugh-Wooley algorithm. This novel structure applied to the fixed-width low-pass digital FIR filter for a speech signal processing system has excellent performance in reducing maximum error, average error, and variation of errors.

A 2.4 GHz CMOS image-reject low noise amplifier

In this paper, a new image-reject low noise amplifier is designed for the 2.4 GHz industrial-scientific-medical (ISM) band. An inter-stage T-structure filter is used in the low noise amplifier design to provide 35 dB image rejection. The goal of this design is to merge the image-reject function into the low noise amplifier.

A One-Step Input Matching Method for Cascode CMOS Low-Noise Amplifiers

In the design of cascode CMOS low-noise amplifiers, the gate-drain capacitance is generally neglected because it is thought to be small enough compared to gate-source capacitance. However, a careful examination will reveal the fact that the drain impedance of the input transistor significantly affects the input impedance through the gate-drain capacitance, especially as the CMOS technology getting more and more advanced. Moreover, the substrate coupling network of the input transistor also comes into play when the drain impedance of the input transistor is high enough compared to the substrate coupling network. In order to make input matching easier, it is desirable to know the details of the substrate coupling network. Unfortunately, designers generally do not have enough information about the technology they have used, not to mention knowing the details concerning the substrate coupling network. As a matter of fact, designers generally do have foundry provided component models that contain information about the substrate coupling network. This gives us the chance to minimize its effect and predict the input impedance of a low noise amplifier more accurately. In this paper, we show that the effect of the substrate coupling network can be ignored by keeping the drain impedance of the input transistor low enough and a proper drain impedance can then be chosen to achieve input matching without the need of iteration steps. Simulation results of a 2.4 GHz CMOS low noise amplifier using foundry provided component models are also presented to demonstrate the validation of the proposed input matching method.

A new VLSI architecture without global broadcast for 2-D digital filters

In this paper, we propose the new two-dimensional (2-D) systolic-array structures of IIR/FIR digital filters without global broadcast by the different derivation and another systolic transformation. For more practical considerations, we further provide a detailed block diagram of a 2-D FIR filter using a recently proposed multiplier to reduce the roundoff quantization error in the logic-gate level. These proposed systolic structures amenable to VLSI implementation permit the 2-D input sequence to be scanned in row-wise mode and locally broadcast one value each clock per delay element.

A tree-systolic array of DLMS adaptive filter

In this work, we develop an optimized binary tree-level rule for the design of a systolic array structure of a delay least mean square (DLMS) adaptive filter. Using the developed method, a higher convergence rate can be obtained without sacrificing the properties of the systolic array structure. Also, based on the optimized tree rule, the user can easily design any even-number tap adaptive system with minimum delay and high regularity under the constraints of maximum driving and the total number of taps.

Pipelining extended givens rotation RLS adaptive filters

In this paper, we propose a new pipelining extended Givens Rotation Recursive Least Square (PEGR-RLS) architecture using look-ahead technique. The square-root-free forms of QRD-RLS are also difficult to pipeline. The PEGR-RLS algorithm (referred to as Scaled Tangent Rotation, STAR-RLS) is designed such that fine-grain pipelining can be accomplished with little hardware overhead. Similar to STAR-RLS, this algorithm is not exactly orthogonal transformations but tends to become orthogonal asymptotically. This algorithm also preserves the desired properties of the STAR-RLS algorithm. Specifically, it can be pipelined at very low forgetting factor by using extended look-ahead. Simulation results are presented to compare the performance of the STAR-RLS, QRD-RLS, and LMS algorithms.

Design of an efficient RAKE receiver architecture for multiuser detection with adaptive channel estimation

In this paper, we propose an efficient implementation scheme of wideband version of parallel interference cancellation (PIC) called regenerative PIC for multiuser detector with Rayleigh fading multipath channel and multiple access interference (MAI). Multiuser detection shall be used in the receiver. The successive PIC scheme cancels the interference of all users simultaneously. The multistage PIC suppresses the multiple access interference in multiple consecutive steps. Stage n cancels the interference by utilizing the hard symbol decision from stage n-1. The cancellation operation itself requires knowledge of the user codes, the relative code phases, complex estimates for the multipath taps, and finally hard symbol decisions for each user.

Design of a normalized delayless LMS adaptive subband digital filter

A new architecture is proposed for the normalized delayless least mean squares (NDLMS) adaptive subband filter. The proposed architecture is based on the hardware-efficient pipelined architecture for the LMS adaptive filter and subband methodology, and it can achieve good convergence characteristics, short latency and high throughput simultaneously without adaptation delays. In addition, it maintains the advantage of the normalised LMS, i.e., the step size assures that the convergence rate is determined automatically. Computer simulation results confirm that the proposed architecture achieves satisfied convergence rate identical to those of the normalised LMS in frequency-domain.

A new 2-D digital filter using a locally broadcast scheme and its cascade form

In this paper, we propose a new two-dimensional (2-D) systolic-array digital filter using a local broadcast scheme that is the hybrid of a modified reordering and another systolic transformation. This architecture occupies local broadcast, lower quantization error and zero latency without sacrificing the number of multipliers as well as delay elements under the accepted critical period. In addition, the widely used 2-D cascaded systolic digital filter can be described and reconstructed by a similar methodology.