Wu-Shiung Feng

New efficient designs for XOR and XNOR functions on the transistor level

Two new methods are proposed to implement the exclusive-OR and exclusive-NOR functions on the transistor level. The first method uses non-complementary signal inputs and the least number of transistors. The other one improves the performance of the prior method but two more transistors are utilized. Both of them have been fully simulated by HSPICE on a SUN SPARC 2 workstation. >

Design of the lower error fixed-width multiplier and its application

This brief develops a general methodology for designing a lower-error twos-complement fixed-width multiplier that receives two n-bit numbers and produces an n-bit product. By properly choosing the generalized index, we derive better error-compensation bias to reduce the truncation error and then construct a lower error fixed-width multiplier, which is area efficient for VLSI implementation. Finally, we successfully apply the proposed fixed-width multiplier to realizing a digital FIR filter, which has shown that the performance is better than that using other fixed-width multipliers.

An efficient systolic architecture for the DLMS adaptive filter and its applications

In this paper, we propose an efficient systolic architecture for the delay least-mean-square (DLMS) adaptive finite impulse response (FIR) digital filter based on a new tree-systolic processing element (PE) and an optimized tree-level rule. Applying our tree-systolic PE, a higher convergence rate than that of the conventional DLMS structures can be obtained without sacrificing the properties of the systolic-array architecture. The efficient systolic adaptive FIR digital filter not only operates at the highest throughput in the word-level but also considers finite driving/update of the feedback error signal. Furthermore, based on our proposed optimized tree-level rule that takes account of minimum delay and high regularity, an efficient N-tap systolic adaptive FIR digital filter can be easily determined under the constraint of maximum driving of the feedback error signal.

A 2.4-GHz CMOS down-conversion doubly balanced mixer with low supply voltage

A CMOS down-conversion mixer with the combination of Gilbert Cell mixer and modified low voltage design technique using LC-tank is demonstrated in this paper. The RF, LO and IF port frequencies are 2.4 GHz, 2.3 GHz and 100 MHz respectively. The measurement results of the proposed mixer exhibit 6.7 dB of conversion gain, -18 dBm of P/sub -1 dB/ compression point and -7.5 dBm of IIP3 with -8 dBm LO power and 1.8 V supply voltage. The power consumption in mixer core is 5.94 mW. This mixer was fabricated in 0.35 um 1P4M CMOS process and the size is 1.5/spl times/1.1 mm/sup 2/. It can provide 0.7 dB conversion gain even though 1.3 V supply voltage is utilized.

An H-V alternating router

An H-V alternating router based on the concurrent H (horizontal) and V (vertical) tile expansions is presented. The router is modeled by a sequence of alternating H and V corner-stitching space tiles, where the expansion direction is controlled by a heuristic evaluation function using the A* technique and the damping concept. Tile growing is governed by the following three factors: constrained expansion area, limited expansion depth, and oriented expansion direction. All the H-V tile expansion operations can be easily performed on a specially designed net-forest structure. It is shown that this approach generates nearly optimal connection paths with a minimum number of bends and always guarantees a feasible solution if such a path exists. The performance of this router is better than that of H-only tile-expansion routers. This router is also well suited for wiring hierarchical modules with the metal-metal matrix technology and can be extended to multilayer layouts. >

Using a multiple storage quad tree on a hierarchical VLSI compaction scheme

A graph-generating algorithm and the experimental results of a hierarchical mask-layout-compaction scheme based on a plane-sweep algorithm, a fast region-query and a space-efficient data structure called the hierarchical multiple-storage quad tree are presented. For a mask-layout design, a rectangle is used as the primary element of the layout. Hence, in the hierarchical mask-compaction scheme, the graph-generating algorithm is based on the edges of rectangles rather than the central lines of symbols for the symbolic-compaction design. The plane-sweep algorithm is also called a dynamic event scheduling algorithm and can be applied to solve some other problems in the field of computational geometry and image processing. The efficiencies of the plane-sweep algorithm and the graph-generating algorithm are dependent on the region-query operations of the spatial data structure. By using the improved multiple storage quad tree as the spatial data structure in the system, the mask-layout compactor has been accomplished in a practically linear time performance in terms of the rectangles in the source layout. >

MOSFET drain breakdown voltage

The grounded-gate or gate-assisted drain breakdown voltage of n-channel MOSFETs has been characterized for wide ranges of oxide thickness and substrate doping concentration. Two distinct regimes, one being channel-doping limited and the other being oxide-thickness limited, have been identified. We propose that these two regimes reflect two possible locations of breakdown-at the n+-p junction and in the deep-depletion layer in the n+ drain. They can be separated by their different breakdown voltage dependences on Vgand require different approaches to process improvement.

Model-order reductions for MIMO systems using global Krylov subspace methods

This paper presents theoretical foundations of global Krylov subspace methods for model order reductions. This method is an extension of the standard Krylov subspace method for multiple-inputs multiple-outputs (MIMO) systems. By employing the congruence transformation with global Krylov subspaces, both one-sided Arnoldi and two-sided Lanczos oblique projection methods are explored for both single expansion point and multiple expansion points. In order to further reduce the computational complexity for multiple expansion points, adaptive-order multiple points moment matching algorithms, or the so-called rational Krylov space method, are also studied. Two algorithms, including the adaptive-order rational global Arnoldi (AORGA) algorithm and the adaptive-order global Lanczos (AOGL) algorithm, are developed in detail. Simulations of practical dynamical systems will be conducted to illustrate the feasibility and the efficiency of proposed methods.

XNOR-based double-edge-triggered flip-flop for two-phase pipelines

The conventional approach of double-edge-triggered flip-flops (DET-FFs) is to have two similar edge-triggered latches. And the achieved faster speed is at the cost of double chip area and complex logic structure. By contrast, the XNOR-based approaches is difficult to reach the speed demand due to the delay of the XNOR -based clock generator. This paper proposes a new designed DET-FF based on an alternative XNOR gate. By utilizing the sensitivity to the driving capacity of the previous stage, we use this simplified XNOR gate as a pulse-generator. A modified transparent latch following the pulse-generator acts as an XNOR-based DET-FF, which accomplishes the almost same speed and less power dissipation as compared with two conventional DET-FFs under HSPICE simulation. We also implemented the XNOR-based DET-FF in a two-phase-pipeline system, and the HSPICE simulation in the TSMC 0.25 um CMOS process shows our proposed DET-FF is much faster than those two conventional DET-FFs.

Relaxation-based transient sensitivity computations for MOSFET circuits

In this paper, we propose two new methods for computing the transient sensitivities of large scale MOSFET circuits, which exploit the relaxation-based circuit simulation techniques, the waveform relaxation (WR) method and the iterated timing analysis (ITA) method. Sufficient conditions are stated and proven, which are quite mild for MOSFET circuits, for convergence of these new methods. A pruning scheme, which prunes the sensitivity circuits, takes the positions of the design parameters as well as the outputs of interest into account and saves any redundant subcircuit computation even though that subcircuit may not be latent. By modifying the original WR and ITA algorithms, we also present practical computational algorithms which can process multiple design parameters. These practical algorithms retain most of the structures of the original algorithms, which can easily be implemented into available relaxation-based circuit simulators. These new methods have been implemented and the experimental results for several circuits are shown to demonstrate their effectiveness. >