Shingo Mandai

Cascaded time difference amplifier using differential logic delay cell

We introduce a 42x cascaded time difference amplifier (TDA) using differencial logic delay cells with 0.18µm CMOS process. By employing differential logic cells for the delay chain instead of CMOS logic cells, our TDA has stable time difference gain (TD gain) and fine time resolution. Measurement results show that our TDA achieves less than 5.5% TD gain offset and ±250ps input range. Also the charge pump current of PMOS and NMOS unbalance can adjust the TD gain.

Time-to-digital converter based on time difference amplifier with non-linearity calibration

This paper proposes a time-to-digital converter (TDC) utilizing the cascaded time difference amplifier(TDA) and shows measurement results with 0.18um CMOS. The proposed TDC operates in two modes, a wide input range mode and a fine time resolution mode. We employ a non-linearity calibration technique based on lookup table. The wide input range mode shows 10.2ps time resolution over 1.3ns input range with DNL and INL of +0.8/−0.7LSB and +0.8/−0.4LSB, respectively. The fine time resolution mode shows 1.0ps time resolution over 60ps input range with DNL and INL of +0.9/−0.9LSB and +0.8/−1.0LSB, respectively.

Multi functional range finder employing a dual imager core on a single chip

This paper presents a multi functional range finder employing dual imager core on a single chip. With a combination of the light-section method and the stereo-matching method, our range finder achieves three modes, which are 2-D imaging mode, high speed 3-D imaging mode and high accuracy 3-D imaging mode. In 2-D imaging mode, 8 bit gray scale imaging speed is 58 fps, in high speed imaging mode, maximum frame rate is 24.8 range maps/s and in high accuracy 3-D imaging mode, maximum range error is 1.619 mm at 700 mm and the standard deviation of measured error is 0.385 mm. Our range finder adopts and can be used selectively according to the circumstances.

A 8bit two stage time-to-digital converter using 16x cascaded time difference amplifier in 0.18um CMOS

We have designed a 8bit two stage time-to-digital converter(TDC) using a time difference amplifier in 0.18um CMOS process. The time resolution is 1.89ps, and DNL of 0.9 and INL of 1.0 are achieved in simulation. To amplify the time residue of the first stage, the 16x cascaded time difference amplifier(TDA) using differential logic delay cells is employed. By using differential logic cells for the delay chain instead of CMOS logic cells, the 16x cascaded TDA realizes stable time difference gain(TD gain) and fine time resolution. The TDA have been fabricated in 0.18um CMOS process. Measurement results show that our TDA achieves 4.4% TD gain offset at 30ps input range, the standard deviation and the maximum error of the difference between the ideal amplified value and measured value is 13.0ps and 30.0ps respectively. The maximum error corresponds to 0.99 LSB. Linearity of the two stage TDC depends on the specifications of a TDA greatly. The linearity of the proposed TDC improved by using the 16x cascaded TDA and using only one TDA in the two stage TDC instead of using a lot of TDAs.

A 8bit two stage time-to-digital converter using time difference amplifier

We propose a 8bit two stage time-to-digital converter (TDC) using a time difference amplifier. The time resolution is 1.89ps, and DNL of 0.9 and INL of 1.0 are achieved in simulation assuming the standard 0.18um CMOS. To amplify the time residue of the first stage, the 16x cascaded time difference amplifier (TDA) using differential logic delay cells is employed. Time resolution of the proposed TDC becomes finer by employing the 16x cascaded TDA and the linearity is improved by using only one TDA in the two stage TDC instead of using a lot of TDAs.