Toru Nakura

Fine-Grain Redundant Logic Using Defect-Prediction Flip-Flops

Chip production yield of 70% can be increased to 91 % by using fine-grain redundant logic in which only the defective portion of the main circuit is switched to a redundant subcircuit block. In addition, defect-prediction flip-flops prevent over 80% of in-field failures caused by latent defects, while maintaining correct operation. All flip-flops are connected via a scan chain, which can be employed to reproduce states used in avoiding defects, and to trace defect points.

All-digital on-chip monitor for PMOS and NMOS process variability measurement utilizing buffer ring with pulse counter

This paper presents an all-digital process variability monitor which utilizes a simple buffer ring with a pulse counter. The proposed circuit monitors the process variability according to a count number of a single pulse which propagates on the buffer ring and a fixed logic level after the pulse vanishes. The proposed circuit has been fabricated in 65nm CMOS process and the measurement results demonstrate that we can monitor the PMOS and NMOS variabilities independently using the proposed monitoring circuit.

Feedforward active substrate noise cancelling technique using power supply di/dt detector

This paper demonstrates a feedforward active substrate noise cancelling technique using a power supply di/dt detector. Since the substrate is tied to the ground line, the substrate noise is closely related to the ground bounce which is caused by di/dt when inductance is dominant on the ground line impedance. The active cancelling technique detects the di/dt of the power supply current and injects an anti-phase signal into the substrate so that the di/dt proportional substrate noise is cancelled out. 34% of the substrate noise reduction was achieved in a test circuit for the first trial. It is theoretically shown that the optimized canceller design will enhance the suppression ratio up to 56%.

Buffer-ring-based all-digital on-chip monitor for PMOS and NMOS process variability and aging effects

In this paper, we propose an all-digital process variability and aging monitor which utilizes a simple buffer ring with a pulse counter. The proposed circuit monitors the process variability according to a count number of a single pulse which propagates on the buffer ring and a fixed logic level after the pulse vanishes. Using the proposed circuit in combination with a simple ring oscillator which monitors its oscillation period, we can calculate the rise and fall delay values and can monitors the variabilities of PMOS and NMOS devices independently. The experimental results of the circuit simulation on 65nm CMOS process indicate the feasibility of the proposed monitoring circuit. The proposed monitoring technique is suitable not only for the on-chip process variability monitoring but also for the infield monitoring of aging effects such as negative bias instability (NBTI) and channel hot carrier (CHC).

A robust pulse delay circuit utilizing a differential buffer ring

In this paper, we propose a pulse delay circuit using a differential buffer ring. The proposed circuit keeps an input pulse propagating on the buffer ring without a degradation of pulse width information. The cross-coupled buffer ring with compensating inverters improves the tolerance to the process variation. The proposed circuit has been implemented using 65nm CMOS process, and the simulation results demonstrate that the proposed circuit keeps an input pulse width independent of the process corner conditions, and the measurement results show that the proposed pulse delay circuit using differential buffer ring is more robust to the process variability than conventional buffer ring.

Cascaded time difference amplifier using differential logic delay cell

We introduce a 42x cascaded time difference amplifier (TDA) using differencial logic delay cells with 0.18µm CMOS process. By employing differential logic cells for the delay chain instead of CMOS logic cells, our TDA has stable time difference gain (TD gain) and fine time resolution. Measurement results show that our TDA achieves less than 5.5% TD gain offset and ±250ps input range. Also the charge pump current of PMOS and NMOS unbalance can adjust the TD gain.

Time-to-digital converter based on time difference amplifier with non-linearity calibration

This paper proposes a time-to-digital converter (TDC) utilizing the cascaded time difference amplifier(TDA) and shows measurement results with 0.18um CMOS. The proposed TDC operates in two modes, a wide input range mode and a fine time resolution mode. We employ a non-linearity calibration technique based on lookup table. The wide input range mode shows 10.2ps time resolution over 1.3ns input range with DNL and INL of +0.8/−0.7LSB and +0.8/−0.4LSB, respectively. The fine time resolution mode shows 1.0ps time resolution over 60ps input range with DNL and INL of +0.9/−0.9LSB and +0.8/−1.0LSB, respectively.

Moebius circuit: dual-rail dynamic logic for logic gate level pipeline with error gate search feature

We have introduced the concept of the Moebius strip into LSI circuit design, realizing 8.4 FO4-Inverter throughput for any kind of digital logic circuit. The Moebius circuit operates in a logic gate level pipeline, and has error detection and error gate search features, using a self-timed architecture.

Multi functional range finder employing a dual imager core on a single chip

This paper presents a multi functional range finder employing dual imager core on a single chip. With a combination of the light-section method and the stereo-matching method, our range finder achieves three modes, which are 2-D imaging mode, high speed 3-D imaging mode and high accuracy 3-D imaging mode. In 2-D imaging mode, 8 bit gray scale imaging speed is 58 fps, in high speed imaging mode, maximum frame rate is 24.8 range maps/s and in high accuracy 3-D imaging mode, maximum range error is 1.619 mm at 700 mm and the standard deviation of measured error is 0.385 mm. Our range finder adopts and can be used selectively according to the circumstances.

Power supply di/dt measurement using on-chip di/dt detector circuit

This paper demonstrates an on-chip di/dt detector circuit. The di/dt detector circuit consists of a spiral inductor under the power supply line which induces a di/dt proportional voltage, and an amplifier which amplifies and outputs the value. The measurement results show that the di/dt detector output and the voltage difference between a resistor have good agreement. The di/dt detector also measures the de-coupling capacitor effects for the di/dt reduction.