Shingo Yoshizawa

Scalable architecture for word HMM-based speech recognition and VLSI implementation in complete system

This paper describes a scalable architecture for real-time speech recognizers based on word hidden Markov models (HMMs) that provide high recognition accuracy for word recognition tasks. However, the size of their recognition vocabulary is small because its extremely high computational costs cause long processing times. To achieve high-speed operations, we developed a VLSI system that has a scalable architecture. The architecture effectively uses parallel computations on the word HMM structure. It can reduce processing time and/or extend the word vocabulary. To explore the practicality of our architecture, we designed and evaluated a complete system recognizer, including speech analysis and noise robustness parts, on a 0.18-/spl mu/m CMOS standard cell library and field-programmable gate array. In the CMOS standard-cell implementation, the total processing time is 56.9 /spl mu/s/word at an operating frequency of 80 MHz in a single system. The recognizer gives a real-time response using an 800-word vocabulary.

Cepstral gain normalization for noise robust speech recognition

The paper describes a robust speech recognition technique which normalizes cepstral gains in order to remove effects of additive noise. We assume that the effects can be expressed by an approximate model which consists of gain and DC components in log-spectrum. Accordingly, we propose cepstral gain normalization (CGN) which normalizes the gains by means of calculating maximum and minimum values of cepstral coefficients in speech frames. The proposed method can extract noise robust features without a priori knowledge and environmental adaptation because it is applied to both training and testing data. We have evaluated recognition performance under noisy environments using the Noisex-92 database and a 100 Japanese city names task. The CGN provides improvements of recognition accuracy at various SNRs compared with combinations of conventional methods.

VLSI Implementation of a 4×4 MIMO-OFDM transceiver with an 80-MHz channel bandwidth

VLSI Implementation for a 4×4 multiple-input multiple-output orthogonal frequency division multiplexing (MIMO-OFDM) transceiver is described that targets 1-Gbps data transmission for next-generation wireless LAN systems. The IEEE802.11 Very High Throughput (VHT) Study Group concluded that a signal bandwidth of more than 80 MHz is needed to achieve 1-Gbps throughput in the MAC layer. The proposed architecture is suitable for VLSI implementation that meets this specification and enables real-time processing in a 4×4 MIMO-OFDM configuration. It incorporates a minimum meansquare error (MMSE) MIMO detector that drastically shortens processing latency. Evaluation of a MIMO-OFDM transceiver implemented in CMOS with 128, 256, or 512 OFDM subcarriers showed that the power dissipation ranged from 451 to 577 mW.

Tunable Wordlength Architecture for a Low Power Wireless OFDM Demodulator

We present a low power architecture that dynamically controls wordlengths in a wireless OFDM demodulator. Finding the optimum wordlength for digital circuit systems is difficult because the trade-off between the hardware cost and system performance is not conclusive. Actual circuit systems have large wordlengths at the circuit design level to avoid calculation errors caused by a lack of dynamic range. This indicates that power dissipation can still be reduced under better conditions. We propose a tunable wordlength architecture that dynamically changes its own wordlength according to the communication environment. The proposed OFDM demodulator measures error vector magnitudes (EVMs) from de-modulated signals and tunes the wordlength to satisfy the required quality of communication by monitoring the EVM performance. The demodulator can reduce dissipated energy by a maximum of 32 and 24% in AWGN and multipath fading channels.

A complete pipelined MMSE detection architecture in a 4x4 MIMO-OFDM receiver

This paper presents a VLSI architecture of MMSE detection in a 4 x 4 MIMO-OFDM receiver. Packet-based MIMO- OFDM imposes a considerable throughput requirement on the matrix inversion because of strict timing in frame structure and subcarrier-by-subcarrier basis processing. Pipeline processing oriented algorithms are preferable to tackle this issue. We adopt Strassens algorithms of matrix inversion and multiplication to circuit design in the MMSE detection. The complete pipelined architecture achieves real-time operation which does not depend on numbers of subcarriers. The designed circuit has been implemented to a 90-nm CMOS process and shows a potential for providing a 2.6-Gbps transmission speed in a 160-MHz signal bandwidth.issue.

Scalable architecture for word HMM-based speech recognition

This paper presents a scalable architecture for realizing real-time speech recognizers based on a word HMM (hidden Markov model). HMM-based recognition algorithms are classified into two acoustic models, i.e., phenome-level model and word-level model. The phenome-level HMM has been widely used in current speech recognition systems which permit large-sized vocabularies. Whereas the word-level HMM has been constrained to small-sized vocabularies because of extremely high computation cost in spite of excellent recognition performance. In order to overcome the shortage, we adopt the scalable architecture focused on the word HMM structure. The proposed architecture can flexibly improve recognition performance and extend word vocabularies. In addition, the computation time is hardly increasing. In order to demonstrate practical solutions, we have designed and evaluated a total system recognizer including speech analysis and noise robustness on a 0.18 /spl mu/m CMOS standard cell library. The recognition time is 35.7 /spl mu/s/word at 128 MHz operating frequency. The recognizer can achieve over middle-sized vocabularies in real-time response.

Tunable word length architecture for low power wireless OFDM demodulator

This paper proposes a low power architecture that dynamically controls a word length in a wireless OFDM demodulator. Finding the optimum word length for digital systems is a difficult problem because the trade-off between hardware cost and system performance is not conclusive. Actual digital systems prepare a more than enough word length in circuit design level to avoid the worst condition caused by lack of dynamic range. It indicates that they still have room to reduce power during better conditions. We propose tunable word length architecture (TWA) that dynamically changes its own word length according to communication environments. The proposed OFDM demodulator measures error vector magnitude (EVM) from de-modulated signals and tunes a word length to satisfy required quality of communication by monitoring the EVM performance. Our result reports that the demodulator reduced dissipated energy by the maximum 32% and 24% in AWGN and multipath fading channels, respectively, compared to use of a fixed word length

300-Mbps OFDM baseband transceiver for wireless LAN systems

This paper presents an OFDM transceiver for wireless LAN systems and its baseband transceiver architecture. We study the optimum parameters about DFT size, guard interval, symbol duration, and number of subcarriers in an 80-MHz bandwidth by extending the IEEE 802.11a standard. The proposed transceiver has a maximum 300-Mbps transmit rate and achieves 600 Mbps by use of a 4times2 MIMO system. We have designed the SISO-OFDM transceiver in a 0.25-mum CMOS technology. The transceiver consumes about 800 mW at 2.5-V power supply and 80-MHz clock frequency. For verification, the architecture has been implemented to a FPGA prototype. We describe the parameters of our proposal and the TGn Sync optional proposal by comparison

Searching phase optimize in PTS-APPR method by GA for PAPR reduction in OFDM-WLAN systems

In this paper, we propose a new PAPR reduction using the hybrid of a partial transmit sequences (PTS) and an adaptive peak power reduction (APPR) methods with genetic algorithm (GA). These methods are used in an Orthogonal Frequency Division Multiplexing (OFDM) system. The OFDM employs orthogonal sub-carriers for data modulation. These sub-carriers unexpectedly present a large Peak to Average Power Ratio (PAPR) in some cases. In order to reduce PAPR, the sequence of input data is rearranged by PTS. The APPR method is also used to controls the peak level of modulation signals by an adaptive algorithm. A proposed reduction method consists of these two methods and realizes both advantages at the same time. In order to make the optimum condition on PTS for PAPR reduction, a quite large calculation cost must be demanded and thus it is impossible to obtain the optimum PTS. In the proposed method by using genetic algorithm, the total calculation cost becomes drastically reduced. The parameter for simulation used standard WLAN in IEEE 802.11a system. In simulation results, the proposed method shows the improvement on PAPR and also reveals the high performance on bit error rate (BER) of an OFDM system.

VLSI Implementation of a Complete Pipeline MMSE Detector for a 4 × 4 MIMO-OFDM Receiver

This paper presents a VLSI architecture of MMSE detection in a 4×4 MIMO-OFDM receiver. Packet-based MIMO-OFDM imposes a considerable throughput requirement on the matrix inversion because of strict timing in frame structure and subcarrier-by-subcarrier basis processing. Pipeline processing oriented algorithms are preferable to tackle this issue. We propose a pipelined MMSE detector using Strassens algorithms of matrix inversion and multiplication. This circuit achieves real-time operation which does not depend on numbers of subcarriers. The designed circuit has been implemented to a 90-nm CMOS process and shows a potential for providing a 2.6-Gbps transmission speed in a 160-MHz signal bandwidth.