Shinji Yamaura

A fully integrated triple-band CMOS power amplifier for WCDMA mobile handsets

The recent rapid spread of smart-phone use has resulted in a strong demand for a multi-band RF part with reduced size and power consumption. In the creation of an ideal RF system-on-a-chip, the biggest challenge is to realize a fully integrated PA in CMOS. In conventional PAs in compound semiconductor technologies, face-up wire-bond assembly with off-chip matching components is typically used, but flip-chip packaging is more suitable for slim mobile phones in which low-profile components are desired as well as for future integration with an RF transceiver in which the same packaging scheme is widely used. The PA for GSM [1] was insufficient for our target, so we needed to greatly improve the linearity in order to comply with the W-CDMA standard, which has better frequency-usage efficiency. Conventional CMOS PAs only support a single band [2,3] or are for WLAN [4] where the output power level is low (typically about 20dBm). In this paper, we present a fully-integrated triple-band linear CMOS PA for W-CDMA. Its flip-chip package is just 3.5×4×0.7mm3, and the average current consumption is less than 20mA.

A 50-Gbit/s 1:4 demultiplexer IC in InP-based HEMT technology

An 80 Gbit/s 1:2 demultiplexer (DEMUX) is presented that was fabricated using 0.1-/spl mu/m-gate-length InP-based HEMT technology. A data input buffer with a common-gate amplifier in front is employed to achieve a low return loss over wide frequency range and to suppress signal distortion, which is mainly caused by multiple reflections between a DEMUX chip and a signal source. A DEMUX core consisting of a D-type flip-flop (FF) and a tri-stage FF assures the edge alignment of two channels of de-serialized signals. The 1:2 DEMUX operated at up to 80 Gbit/s, which was limited by our measurement equipment. At that bit-rate, the input sensitivity and clock phase margin estimated from monitoring eye-openings were about 100 mVp-p and 160 degrees, respectively. The skew of the two output signals was only 2 ps.We have developed a 50-Gb/s 1:4 demultiplexer (DEMUX) integrated circuit with a wide phase margin of 108 degrees in 0.13-/spl mu/m InP-based HEMT technology. To increase the phase margin, we designed the data and clock distribution with the aim of achieving high symmetry and eliminating multiple reflections. The measured performance of the fabricated 1:4 DEMUX was suitable for practical use in 50-Gbit/s-class applications.

High RF power transistor with laterally modulation-doped channel and self-aligned silicide in 45nm node CMOS technology

A novel high RF power MOSFET was developed to integrate a high-power amplifier into 45 nm node CMOS technology. A self-aligned silicide and laterally modulation-doped channel attained the lowest on-resistance of 1.7 Omega-mm with a high breakdown voltage of more than 10 V and successfully achieved the highest output power density of 0.6 W/mm at the maximum power-added efficiency ever reported among CMOS high breakdown voltage transistors. The reduced gate resistance led to a high frequency characteristic of 43 GHz fmax. We also confirmed that the optimized profile of a gate-overlapped lightly doped drain provides sufficient HC and TDDB reliabilities with a gate oxide as thin as a 3.3 V I/O transistor. These results indicate that a single-chip CMOS transceiver with a high-power amplifier can be produced in advanced CMOS fabs.

A 50-Gbit/s 450-mW Full-Rate 4:1 Multiplexer With Multiphase Clock Architecture in 0.13-

A full-rate multiplexer (MUX) with a multiphase clock architecture for over 40 Gbit/s optical communication systems is presented. The 4:1 MUX is comprised of a re-timer based on a D-type flip-flop (DFF) and a clock tree system that uses EXOR-type delay buffers to match its skews well to those of the data. The supply voltage is reduced to -1.5 V by analyzing the voltage allocation. Fabricated in a 0.13-mum InP HEMT technology, a DFF test circuit achieved 75-Gbit/s operation and exhibited performance sufficient to re-time 50-Gbit/s serialized data. The 4:1 MUX measurement results demonstrate successful 50-Gbit/s operation at room temperature, and 40-Gbit/s operation, which has 10-11 error free for 231 - 1 pseudorandom bit stream (PRBS) data, up to an ambient temperature of 90 degrees or down to - 1.24 V of supply voltage. The circuit consumes 450 mW at a - 1.5-V supply and exhibits an output jitter of 283 fs rms at 50-Gbit/s operation. We also propose a multiphase clock generator for a MUX that has a serialization of more than four channels.

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An on-chip CMOS RF power detector (PD) is described that has internal temperature compensation and the highest reported linearity. The PD generates a DC current that is proportional to the square root of the RF input power by use of a new detection technique that utilizes p-n junction diodes. The generated DC current obtained by subtracting a replicated current produces the real-time temperature compensation. This subtraction method also suppresses the generated-current error caused by the parasitic element, thereby improving the linearity of the PD. The proposed on-chip PD was fabricated in 90-nm CMOS technology and integrated with a power amplifier (PA). The measured input range for a linearity error within ±0.5 dB was 27 dB at 0.824 GHz and 23 dB at 1.98 GHz. The measured results showed that the PD overcomes real-time temperature changes caused by self-heating, which depends on the output power of the PA. The PD consumes 0.3 mW at 0-dBm input power and occupies 0.04 mm2, which are small enough for the PA.

InP HEMT Technology

Recent progress in the multi-wafer CBE system has demonstrated the potential capability of producing the state-of-the-art compound semiconductor devices with excellent uniformity and reproducibility. The Al compositional uniformity of three 4 inch wafers grown at the same time is 0.2136 ± 0.0014 (standard deviation). The uniformity in thickness, composition, carrier concentration for three 3 inch wafers is within ±1.8%, ± 0.003 (Ga in InGaP), and ±2.2%, respectively. The temperature variation across a 3 inch GaAs wafer is ±0.9°C. The extreme abruptness of composition and the doping profiles using gaseous dopant sources are another remarkable advantage of this growth system. The extremely low surface defect density of 2.8 cm -2 for GaAs is routinely obtained. The InGaP/GaAs heterojunction bipolar transistor (HBT) with high current gain and superior high-frequency characteristics of excellent uniformity is successfully fabricated. These remarkable results are ascribed to the unique and superior design of the overall growth system : i.e. the novel metalorganic gas cells with the tilted aperture without any diffuser, the improved In-free substrate holder, the completely shut-off shutters, and the gas handling system.

A real-time temperature-compensated CMOS RF on-chip power detector with high linearity for wireless applications

In recent years, the demand for low cost and system-on-a-chip for mobile terminals has led to the development of a highly-integrated, low-distortion, and high-power-efficiency CMOS power amplifier (PA). To improve the power efficiency of the conventional linear PA [1-4], an envelope tracking (ET) technique, which modulates supply voltage of a linear PA, has attracted attention. However, the published power efficiency, gain and output power are not sufficient for LTE applications [5], and its typical implementation requires an external supply modulator that is a high-speed power supply circuit [6]. Envelope elimination and restoration (EER) is an alternative supply modulation technique that can further improve the power efficiency over ET by replacing the linear PA with a switching PA driven by a phase signal [7]. However, to meet the specified low distortion, especially for LTE with a wide bandwidth baseband signal, an EER PA generally has difficulty achieving a wide bandwidth for the phase signal path, and requires a high-speed supply modulator, and highly accurate timing between envelope and phase signals. To overcome these problems, this paper introduces an envelope / phase generator based on a mixer and a timing aligner based on a delay-locked loop. Additionally, they were integrated with a switching PA and a supply modulator on the same die.

Recent progress in the multi-wafer CBE system

Abstract We report for the first time on the high quality and highly uniform InGaP/GaAs heterojunction bipolar transistors with a carbon-doped base grown by a multi-wafer gas-source molecular beam epitaxy (GSMBE) system, which was developed by ourselves. A large-area uniform growth of p-type GaAs and InGaP has been realized. The variation in layer thickness of these layers was less than ± 1.8% across three 3-inch wafers. A large-area (200 × 200 μm 2 ) heterojunction bipolar transistor (HBT) with a base-sheet resistance of 350 Ω showed a high current gain of 190. This is effectively the highest value considering the base sheet resistance, and is comparable to the best data of AlGaAs/GaAs HBTs reported so far. The small signal current gains showed an excellent uniformity of 3% across one of five 2-inch wafers. The wafer-to-wafer variation of current gains for the two 2-inch wafers, in the same growth run, was less than 3%. The base sheet resistances also showed an excellent uniformity of 0.86%. In addition the average base sheet resistances of the two 2-inch wafers was the same. The device also showed an excellent high-frequency characteristics. The cut-off frequency ( f t ) of 61 GHz, and the maximum-oscillation frequency ( f max ) of 94 GHz were obtained for the transistor having a base dopant concentration of 4 × 10 19 cm −3 . These promising results demonstrate the high potential capability of multi-wafer GSMBE for the production of InGaP/GaAs HBTs.

3.2 A 1.95GHz fully integrated envelope elimination and restoration CMOS power amplifier with envelope/phase generator and timing aligner for WCDMA and LTE

We fabricated a multiband transceiver for mobile WiMAX in 90-nm CMOS technology. It operates at three RF bands (2.3/2.5/3.5 GHz) with a large dynamic range. We adopted a double conversion receiver that can switch lower and upper local modes. An image rejection ratio (IRR) tunable single side-band (SSB) mixer was used to achieve over 50 dB IRR. The RCE for 2.5 GHz at −71.5 dBm input was −28.7 dB and maximum input level up to −20 dBm was achieved using variable gain LNAs and mixers. The transmitter had a dynamic range of over 56 dB.

High current gain InGaP/GaAs heterojunction bipolar transistors grown by multi-wafer gas-source molecular beam epitaxy system

A high-efficiency CMOS power amplifier (PA) based on envelope tracking (ET) has been reported for a wideband code division multiple access (W-CDMA) and long term evolution (LTE) application. By adopting a high-speed CMOS envelope amplifier with current direction sensing, a 5% improvement in total power-added efficiency (PAE) and a 11 dB decrease in adjacent channel leakage ratio (ACLR) are achieved with a W-CDMA signal. Moreover, the proposed PA achieves a PAE of 25.4% for a 10 MHz LTE signal at an output power (Pout) of 25.6 dBm and a gain of 24 dB.