Hideki Kano

A 1-Gb SDRAM with ground-level precharged bit line and nonboosted 2.1-V word line

A dramatic reduction of the internal operating voltage and a high-speed clocking technique are the keys to low-power, high-speed memory technologies. When the memory core supply voltage is reduced to below 1.8 V, the electrical performance significantly degrades in two ways. First, sensing speed slows due to the noticeable threshold voltage of source-floated transistors. Second, the necessity of a relatively high Vpp voltage for the word lines may require a tripler-pumping circuit that significantly increases power. In this 1 Gb synchronous DRAM, the bitline precharge level is Vss (ground). The word line reset level is -0.5 V to prevent cell leakage current while reducing the threshold voltage of pass transistors and thus to eliminate word line boosting. Power consumption is thus decreased since inefficient tripler boosting is no longer necessary. This technology is also suitable for merged DRAM and logic circuits.

A fully integrated triple-band CMOS power amplifier for WCDMA mobile handsets

The recent rapid spread of smart-phone use has resulted in a strong demand for a multi-band RF part with reduced size and power consumption. In the creation of an ideal RF system-on-a-chip, the biggest challenge is to realize a fully integrated PA in CMOS. In conventional PAs in compound semiconductor technologies, face-up wire-bond assembly with off-chip matching components is typically used, but flip-chip packaging is more suitable for slim mobile phones in which low-profile components are desired as well as for future integration with an RF transceiver in which the same packaging scheme is widely used. The PA for GSM [1] was insufficient for our target, so we needed to greatly improve the linearity in order to comply with the W-CDMA standard, which has better frequency-usage efficiency. Conventional CMOS PAs only support a single band [2,3] or are for WLAN [4] where the output power level is low (typically about 20dBm). In this paper, we present a fully-integrated triple-band linear CMOS PA for W-CDMA. Its flip-chip package is just 3.5×4×0.7mm3, and the average current consumption is less than 20mA.

A 43-Gb/s full-rate-clock 4:1 multiplexer in InP-based HEMT technology

A 43 Gb/s 4:1 multiplexer in 0.13/spl mu/m InP-based HEMT technology contains a 52 Gb/s static D-FF and a phase adjuster giving the D-FF 360/spl deg/ effective phase margin. Microwave techniques and optimization of layout enable 43 Gb/s operation with 43 GHz full-rate clock. Power dissipation is 7.9 W at -5.2 V.

A 1.95 GHz Fully Integrated Envelope Elimination and Restoration CMOS Power Amplifier Using Timing Alignment Technique for WCDMA and LTE

A fully integrated envelope elimination and restoration (EER) CMOS power amplifier (PA) has been developed for WCDMA and LTE handsets. EER is a supply modulation technique that first divides modulated RF signal into envelope and phase signals and then restores it at a switching PA output. Supply voltage of the switching PA is modulated by the envelope signal through a high-speed supply modulator. EER PA is highly efficient due to the switching PA and the supply modulation. However, it generally has difficulty, especially for a wide bandwidth baseband application like LTE, achieving a wide bandwidth for phase signal path and highly accurate timing between envelope and phase signals. To overcome these challenges, an envelope/phase generator based on a mixer and a limiter was proposed to generate the wide bandwidth phase signal, and a timing aligner based on a delay locked loop with a variable high-pass filter (HPF) was proposed to compensate for the timing mismatch. The chip was implemented in 90 nm CMOS technology. Measured power-added efficiency (PAE) and adjacent channel leakage ratio (ACLR) were 39% and -41 dBc for WCDMA, and measured PAE and ACLR E-UTRA1 were 32% and -33 dBc for 20 MHz-BW LTE.

A 50-Gbit/s 1:4 demultiplexer IC in InP-based HEMT technology

An 80 Gbit/s 1:2 demultiplexer (DEMUX) is presented that was fabricated using 0.1-/spl mu/m-gate-length InP-based HEMT technology. A data input buffer with a common-gate amplifier in front is employed to achieve a low return loss over wide frequency range and to suppress signal distortion, which is mainly caused by multiple reflections between a DEMUX chip and a signal source. A DEMUX core consisting of a D-type flip-flop (FF) and a tri-stage FF assures the edge alignment of two channels of de-serialized signals. The 1:2 DEMUX operated at up to 80 Gbit/s, which was limited by our measurement equipment. At that bit-rate, the input sensitivity and clock phase margin estimated from monitoring eye-openings were about 100 mVp-p and 160 degrees, respectively. The skew of the two output signals was only 2 ps.We have developed a 50-Gb/s 1:4 demultiplexer (DEMUX) integrated circuit with a wide phase margin of 108 degrees in 0.13-/spl mu/m InP-based HEMT technology. To increase the phase margin, we designed the data and clock distribution with the aim of achieving high symmetry and eliminating multiple reflections. The measured performance of the fabricated 1:4 DEMUX was suitable for practical use in 50-Gbit/s-class applications.

3.5 A 56Gb/s NRZ-electrical 247mW/lane serial-link transceiver in 28nm CMOS

With the rapid growth of data traffic in data centers, data rates over 50Gb/s/signal (e.g., OIF-CEI-56G-VSR) will eventually be required in wireline chip-to-module or chip-to-chip communications [1-3]. To achieve better power efficiency than that of existing 25Gb/s/signal designs, a high-speed yet energy-efficient front-end is needed in both the transmitter and receiver. A receiver front-end with baud-rate architecture [1] has been successfully operated at 56Gb/s, but additional components such as eye-monitoring comparators, phase detectors, and clock recovery circuitry as well as a power-efficient transmitter are needed to build a complete transceiver.

3.2 A 1.95GHz fully integrated envelope elimination and restoration CMOS power amplifier with envelope/phase generator and timing aligner for WCDMA and LTE

In recent years, the demand for low cost and system-on-a-chip for mobile terminals has led to the development of a highly-integrated, low-distortion, and high-power-efficiency CMOS power amplifier (PA). To improve the power efficiency of the conventional linear PA [1-4], an envelope tracking (ET) technique, which modulates supply voltage of a linear PA, has attracted attention. However, the published power efficiency, gain and output power are not sufficient for LTE applications [5], and its typical implementation requires an external supply modulator that is a high-speed power supply circuit [6]. Envelope elimination and restoration (EER) is an alternative supply modulation technique that can further improve the power efficiency over ET by replacing the linear PA with a switching PA driven by a phase signal [7]. However, to meet the specified low distortion, especially for LTE with a wide bandwidth baseband signal, an EER PA generally has difficulty achieving a wide bandwidth for the phase signal path, and requires a high-speed supply modulator, and highly accurate timing between envelope and phase signals. To overcome these problems, this paper introduces an envelope / phase generator based on a mixer and a timing aligner based on a delay-locked loop. Additionally, they were integrated with a switching PA and a supply modulator on the same die.

A 28-Gb/s 4.5-pJ/bit transceiver with 1-tap decision feedback equalizer in 28-nm CMOS

A low-power and area optimized 28-nm CMOS 28-Gb/s transceiver is presented. The transceiver comprised with one PLL shared with 4 transceiver lanes. To meet the CEI-28G-VSR and CAUI4 (chip-to-module) standards, a 1-tap DFE is employed for the receiver. The power reduction is realized by employing 1-tap loop unrolled DFE circuits with domino logic and dynamic latches, and eliminating FFE. The transceiver occupies 2.31 mm2 and consumes 505 mW (4.5 pJ/bit).

A 28.3 Gb/s 7.3 pJ/bit 35 dB backplane transceiver with eye sampling phase adaptation in 28 nm CMOS

28.3 Gb/s transceiver with 35 dB channel loss equalization is presented. The transmitter deploys 3-tap feed forward equalizer (FFE). The driver employs the hybrid architecture of low voltage differential signaling (LVDS) and source-series-terminated (SST) driver which enables the low power consumption and output signal amplitude fine tune. The receiver comprised with continuous time linear equalizer (CTLE) and 2-tap loop unrolled decision feedback equalizer (DFE). It saves the power consumption by not applying DFE at the eye edge, and increases the eye margin with adaptive sampling clock phase adjustment capability. The transceiver is composed of one PLL and four lanes, occupies 1.67 mm2 and consumes 829 mW (7.3 pJ/bit).