Shinyoung Park

Chip-level wireless power transfer scheme design for next generation wireless interconnected three-dimensional integrated circuits

In this paper, we propose chip-level wireless power transfer (WPT) scheme for the next generation high density wireless three-dimensional (3-D) semiconductor packaging technology. We designed a transmitter coil on an active silicon interposer embedded in a PCB-package and a receiver coil on a processor die. The proposed WPT scheme used magnetic-field resonance coupling for high power transfer efficiency. We fabricated a full-bridge rectifier and a low-dropout regulator (LDO) to make a stable DC power for a voltage-controlled oscillator (VCO) on the processor die using SK/Hynix 0.18 μm CMOS process. A VCO is key circuit block consisting of a PLL for clock generation to synchronize data transfer between a processor and a memory controller. The designed VCO successfully generated 1.6 GHz signal using the power from the proposed chiplevel WPT scheme.

High-Frequency Modeling and Signal Integrity Analysis of a Silicone Rubber Socket for High-Performance Package

As a demand for electrical systems with a wide data bandwidth has increased, high-performance packages ensuring high data rates, such as low power double data rate series, have become common. The need for high-performance test sockets has also emerged to test these packages. However, a conventional pogo pin socket has a limited test bandwidth due to the parasitic components arising from its spring. On the other hand, a silicone rubber socket satisfies the wide bandwidth requirement because it has low parasitic components due to high-density conductive metal powders in an elastic silicone rubber. In this paper, we propose an RLGC equivalent circuit model of a silicone rubber socket and first experimentally verify it. The proposed model is experimentally verified in the frequency domain by comparing the insertion loss obtained from the proposed model to the measurement up to 20 GHz. The proposed model is experimentally verified in the time domain by comparing the eye diagrams obtained from the proposed model to the measurement at a data rate of 12.5 Gb/s. Also, the insertion loss of the sockets with varied height, diameter, and pitch is analyzed using the proposed model. The proposed model provides physical insight of a silicone rubber socket, and it allows to determine whether a socket is reliable for testing high performance packages in a short time. It also gives us the idea how to design a high-performance test socket. Furthermore, we discuss the current capacity and life cycle of the silicone rubber socket in terms of signal integrity as well.

Multi-layer probe card design with signal/power integrity for wafer-level AP test in LPDDR4 channel

In this paper, a vertical probe card consisting of a probe head and a multi-layer ceramic (MLC) board is designed to test wafer-level mobile application processor (AP) chips under LPDDR4 channel specifications. Compared with previously designed probe cards, the newly developed probe card improves signal and power integrity to guarantee the wafer-level AP chips to be operated at 3.2 Gbps speed. In this paper, we propose insertion of ground cobra-shaped needles and ground sheets in the probe head to reduce crosstalk noise and secure return current path. In the far-end crosstalk (FEXT) noise and eye-diagram simulations, FEXT noise in the proposed probe head is suppressed up to 20 dB at 1.6 GHz, and the eye-open size is increased from 18.3 % to 56.6 % at 1.6 Gbps of speed. Measurements are also conducted and well correlated with the simulation results. In MLC board design, ground vias are complemented to near every signal via transitions for improved signal and power integrity. In eye-diagram simulation, eye-opening voltage is enlarged to 65.8 % at 3.2 Gbps. In addition, over 500 of 1 uF decoupling capacitors are implemented on the top layer and the bottom side of the board to lower power distribution network (PDN) impedance. To reduce parasitic inductance on PDN for the memory power supplies, some power planes are repositioned to upper layers of the board. The PDN impedance curves of the memory power domains are lowered by nearly 20 dB above the GHz range. In at-speed test for mobile AP, the designed probe card operates well up to 3.1 Gbps which is the world-wide fastest speed in wafer-level test using a probe card.

PCB-package to chip wireless power transfer scheme using magnetic-field resonance coupling for high-density 3-D IC

In this paper, we propose and demonstrate a chip-level wireless power transfer (WPT) interconnection scheme to reduce power supply interconnections for high-density 3-dimensional integrated circuits (3-D ICs). We fabricated an active chip to design a receiver coil, full-bridge rectifier and DC/DC converter to get DC power from wirelessly delivered AC power from a printed circuit board (PCB) package using the 0.18 μm SK-Hynix CMOS process. The fabricated chip is attached on the transmitter PCB-package with coil-to-coil center alignment for experimental demonstration. An equivalent circuit model of the proposed chip-level WPT interconnection scheme is suggested with analytic equations, and voltage transfer ratio and power transfer efficiency are estimated from the model. The proposed model is verified by comparing Z-parameter results obtained from 3-D EM simulation and measurement of the fabricated test vehicle from 10 MHz to 5 GHz. The voltage transfer ratio and power transfer efficiency of the designed package-to-chip WPT including a 3.3 ohm source resistance is able to reach 0.76 V/V and 34 %, respectively.

Probe Card Design with Signal and Power Integrity for Wafer-Level Application Processor Test in LPDDR Channel

In this paper, a vertical probe card design for wafer-level mobile application processor (AP) chip test is proposed under LPDDR4 channel specifications. The probe card consists of a probe head and a multi-layer ceramic (MLC) board, and it is designed to have signal and power integrity to guarantee the wafer-level AP chips to be operated at 3.2 Gbps of speed under 1.1 V of supply voltage. We proposed insertion of additional ground cobra-shaped needles insertion in the probe head to reduce crosstalk noise and secure return current path. In the far-end crosstalk (FEXT) noise simulation and eye-diagram simulation, FEXT noise in the proposed probe head is suppressed 20 dB at 1.6 GHz, and the eye-open size is increased from 17.9 % to 83.3 % at 1.6 Gbps of speed. Measurements are also conducted and well correlated with the simulation results. In MLC board design, over 500 number of 1 uF decoupling capacitors are implemented on the top layer and the bottom side of the board to lower power distribution network (PDN) impedance. In addition, some power planes for LPDDR memory power supplies are repositioned to upper layers of the board. The PDN impedance curves of the memory power domains are lowered by nearly 20 dB at frequencies above the GHz range. To validate the proposed methods, the original and the revised probe card are compared in the frequency-and time-domain simulations. S-parameters of the probe head are extracted from 3-D EM simulation, and those of the MLC board are extracted from SIwave simulation. For exact eye-diagram simulations, eye-mask information and various conditions of LPDDR4 channel are referred to JEDEC standard.

High-frequency modeling and signal integrity analysis of high-density silicone rubber socket

In this paper, we propose and analyze an equivalent RLGC model of silicone rubber socket with single-ended signaling. A silicone rubber socket consists of highly dense metal powders in elastic silicone rubber. When the silicone rubber is compressed, metal powders form a column which corresponds to a pad of package. Thus, it can be modeled as a pair of cylinders. We have successfully verified the proposed model using a 3D electromagnetic (EM) solver in frequency domain and the eye diagram measurement in time domain. As a result, the verified model can be used to determine whether socket is applicable to the test system in the simulation level concurrently with offering physical insight and reducing time spent 3D EM simulating socket.

Audio frequency ground integrity modeling and measurement for a TDMA smartphone system

In this paper, we first propose a ground network model of an arbitrary shaped multi-layer printed circuit board (PCB)/chassis for accurate and efficient analysis of audio frequency ground noise coupled from a time division multiple access (TMDA) RF power amplifier (PA) to an audio circuit in a smartphone system. We designed test vehicles with varied extent in the ground noise coupling. We successfully verified the proposed model by comparing the ground noise coupling levels obtained from the model, 3-D electromagnetic (EM) simulation and measurement in time and frequency domain. We further discussed the performance of the proposed model by comparing the accuracy of its transfer ground impedance (ZG12) and analysis time with those of from the EM simulation. The proposed model showed high performance with the ZG12 agreed 91.7 % with the EM simulation, and the analysis time 95.5 % reduced compared to the simulation.

Active Silicon Interposer Design for Interposer-Level Wireless Power Transfer Technology for High-Density 2.5-D and 3-D ICs

In this paper, we first propose and demonstrate an interposer-level wireless power transfer (WPT) scheme to reduce the number of wired power supply interconnections for high-density silicon interposer-based 2.5-D and 3-D integrated circuits (2.5-D and 3-D ICs). We first suggest the concept of an active silicon interposer, fabricate it with active circuits for WPT, and finally proved its WPT operation. The active circuits are the rectifier and dc-dc converter designed with 0.18-μm SK-Hynix CMOS process to convert wirelessly delivered ac power from a printed circuit board (PCB) package into dc power. We improved the power transfer efficiency by applying magnetic field resonance coupling with proper coil structure selection. The equivalent circuit model of the WPT interconnection scheme is suggested with analytic equations. For experimental demonstration, the fabricated active silicon interposer is attached on PCB package. The average dc output voltage of the designed CMOS rectifier with an MIM smoothing capacitor was measured 2.21 V, and that of the designed dc-dc converter was measured 1 V, which is a suitable voltage level for 1 V devices in 2.5-D and 3-D ICs.