Manho Lee

Electrical Design of Through Silicon Via

Through Silicon Via (TSV) is a key technology for realizing three-dimensional integrated circuits (3D ICs) for future high-performance and low-power systems with small form factors. This book covers both qualitative and quantitative approaches to give insights of modeling TSV in a various viewpoints such as signal integrity, power integrity and thermal integrity. Most of the analysis in this book includes simulations, numerical modelings and measurements for verification. The author and co-authors in each chapter have studied deep intoTSV for many years and the accumulated technical know-hows and tips for related subjects are comprehensively covered.

Thermal effects on through-silicon via (TSV) signal integrity

The thermal effect on through-silicon via (TSV) noise coupling and S21 of TSV channel were measured in both frequency and time domain from corresponding TSV based passive chips. These measurement results are analyzed using the temperature-dependent TSV lumped model to TSV channel and shows good correlation with measurement. Under the hundreds-of-MHz frequency range, increasing temperature decreases the S21 of TSV channel, but over that frequency range, increasing temperature increases the S21. These phenomena are explained from the model which thermal dependence of the materials is applied.

Noise coupling of through-via in silicon and glass interposer

The noise coupling between signal through-vias of silicon-based interposer and glass-based interposer are compared by simulating in both frequency and time domain. In addition to noise coupling, through-vias S21 in both interposers is also simulated and compared. To obtain reasonable data, all dimension parameters are chosen based on existing recent technology and material properties are also chosen based on further chip manufacturing. With these simulations, it is observed that the glass interposer shows better noise blocking performance, and some important features between silicon and glass interposer are qualitatively explained through previous through-via model.

Temperature-dependent through-silicon via (TSV) model and noise coupling

The effect of temperature variation on through silicon via (TSV) noise coupling is measured in this paper. The measurement result is analyzed using the temperature-dependent TSV lumped model and shows good correlation. Under the hundreds-of-MHz frequency range, increasing temperature reduces the noise suppression because the dielectric constant increases. However, over that frequency range, increasing temperature increases the noise suppression because the silicon substrates resistivity increases.

Noise coupling analysis between TSV and active circuit

This paper investigates about the noise coupling between signal TSV and active circuit in frequency domain using 3D EM solver. Because the active circuits and TSV are generally surrounded by deep N-well and substrate ties, some parameters related to dimension parameters of those are varied to clarify the tendency, and the results are explained qualitatively. After that, using S-parameter, simple MOS application is simulated in time domain simulation.

High-speed probe card design to reduce the crosstalk noise for wafer-level test

With the rapid miniaturization of integrate circuit (IC) chip, wafer-level IC testing has become an important process in the semiconductor industry. The improvements of a vertical probe card allow the test to high speed and high-density devices with short probe length and fine pitch compared to conventional probe cards. Regradless these strength, signal degradation by crosstalk noise in probe card has arisen with smaller pad sizes, multi parallel testing, and increased signal input/output frequencies. Therefore, an analysis of crosstalk noise in probe card structure is necessary. In this paper, we propose a new probe card structure to reduce crosstalk noise by lowering the impedance of the ground return path. The proposed structure is analyzed in the frequency- and time-domains. It is designed with a 3D electromagnetic solver and the results are visualized through S-parameter curves up to 10 Gb/s and eye-diagrams at 1.6 Gb/s. To validate the effect, the original structure and the proposed structure are compared. Through frequecy - and time domain simulation results, we verified that the proposed structure successfully reduces the crosstalk noise.

Through silicon via (TSV) noise coupling effects on RF LC-VCO in 3D IC

Through silicon via (TSV) based 3-dimensional integrated circuit (3D IC) has become the key solution to satisfy continuously increasing demands for small form factor, wide bandwidth, high performance, and low power consumption on electronic devices. However, there still remain several challenges to be solved; one of the most significant issues in 3D IC is TSV to active circuit noise coupling. In this paper, we analyzed the noise coupling between TSV and LC-VCO, which is an important component in RF communication system. When TSV is located near LC-VCO, the noise can easily travel through silicon substrate to the body of MOSFETs in LC-VCO. The noise coupling mechanisms of TSV to PMOS and NMOS are analyzed by voltage transfer functions in frequency-domain obtained by 3D electromagnetic solver simulation. The voltage transfer function between TSV and MOS is analyzed under variations of several physical parameters to clarify the tendencies of noise coupling. In addition, the noise coupling effect on PMOS and NMOS in LCVCO are investigated and compared in terms of sensitivity, such as phase noise.

Audio frequency ground integrity modeling and measurement for a TDMA smartphone system

In this paper, we first propose a ground network model of an arbitrary shaped multi-layer printed circuit board (PCB)/chassis for accurate and efficient analysis of audio frequency ground noise coupled from a time division multiple access (TMDA) RF power amplifier (PA) to an audio circuit in a smartphone system. We designed test vehicles with varied extent in the ground noise coupling. We successfully verified the proposed model by comparing the ground noise coupling levels obtained from the model, 3-D electromagnetic (EM) simulation and measurement in time and frequency domain. We further discussed the performance of the proposed model by comparing the accuracy of its transfer ground impedance (ZG12) and analysis time with those of from the EM simulation. The proposed model showed high performance with the ZG12 agreed 91.7 % with the EM simulation, and the analysis time 95.5 % reduced compared to the simulation.

Design of on-chip linear voltage regulator module and measurement of power distribution network noise fluctuation at high-speed output buffer

By applying on-chip linear VRM, PDN inductance is greatly decreased and PDN resonance peak disappears, which is usually generated by PCB/PKG inductance and on-chip capacitance. To confirm, we design an application circuits which have on-chip linear voltage regulator module (VRM) with aggressor and victim buffer. We validate the advantages of on-chip linear VRM by measuring fabricated chip in this research. Moreover, we show PDN self-impedance at output buffer by simulation with designed PCBs S-parameter, and eye-diagram power fluctuation up to 1 Gbps.

High-Frequency Temperature-Dependent Through-Silicon-Via (TSV) Model and High-Speed Channel Performance for 3-D ICs

Noise coupling through the substrate or silicon interposer among adjacent TSVs has a significant impact on the signal integrity of the TSVs. Since resistance and capacitance are dependent on temperature, more accurate electrical models for TSVs should incorporate the temperature dependency of the material. This paper presents high-frequency temperature-dependent RLGC models for two neighboring TSVs and for two neighboring TSV channels. After validating the models against data measured from a fabricated test vehicle, the paper investigates the impact of temperature on noise coupling between TSVs and TSV channels.