Shiri Moran

Gating Aware Error Injection

Error injection is one of the most commonly used techniques for estimating the reliability of a given hardware design. While error injection in dynamic simulation is widely used in the industry, other methods exist as well, e.g. hardware error injection and fault-tolerance analysis using formal verification. As covering the entire space of all possible fault injections is impractical, nearly all workload-based error injection methods (e.g. simulation or emulation techniques) use a statistical approach for error injection, i.e. they only inject a fraction of all possible faults. As a result, the statistical fault injection approach is much more efficient in characterizing the overall reliability of the design than in finding particular reliability-related bugs. On the other hand, the formal-based approach guarantees full coverage of the design space, including under all possible faults, granted the formal analysis can be completed. However, performing formal verification on design hierarchies with error detection and recovery logic is usually unfeasible. To address the challenge of effectively finding reliability-related bugs on large industrial designs, this paper proposes a novel approach which is aimed at finding a particular kind of design bugs related to gating conditions which correspond to error detection logic. We present an automated method for identifying those gating conditions and generating a gating-aware fault injection module. Experimental results on a real microprocessor arithmetical unit demonstrates the effectiveness of our method in finding real design bugs using relatively small amount of error injection tests.

Designing reliable cyber-physical systems overview associated to the special session at FDL'16

CPS, that consist of a cyber part – a computing system – and a physical part – the system in the physical environment – as well as the respective interfaces between those parts, are omnipresent in our daily lives. The application in the physical environment drives the overall requirements that must be respected when designing the computing system. Here, reliability is a core aspect where some of the most pressing design challenges are: monitoring failures throughout the computing system, determining the impact of failures on the application constraints, and ensuring correctness of the computing system with respect to application-driven requirements rooted in the physical environment. This paper provides an overview of techniques discussed in the special session to tackle these challenges throughout the stack of layers of the computing system while tightly coupling the design methodology to the physical requirements.

Designing Reliable Cyber-Physical Systems

Cyber-physical systems, that consist of a cyber part—a computing system—and a physical part—the system in the physical environment—as well as the respective interfaces between those parts, are omnipresent in our daily lives. The application in the physical environment drives the overall requirements that must be respected when designing the computing system. Here, reliability is a core aspect where some of the most pressing design challenges are: monitoring failures throughout the computing system, determining the impact of failures on the application constraints, and ensuring correctness of the computing system with respect to application-driven requirements rooted in the physical environment.

Designer-level verification: an industrial experience story

Designer-level verification (DLV) is now widely accepted as a necessary practice in the hardware industry. More than ever, logic designers are held responsible for the initial validation of modules they develop, before these are released to systematic verification. DLV requires specific tools and methods adapted for designers, who are not full-time verification experts. We present user experience stories and usage statistics, describing how DLV has been practiced in our company, using a dedicated tool developed for this purpose. A typical pattern that emerges is of designers devoting short, fragmented time periods to DLV work, interleaved with other logic development tasks. We observe that the deployed DLV tool supports this mode of work, since it is simple and intuitive. This demonstrates that a suitable tool can help DLV become an integral part of a logic design project.