Shishpal Rawat

EDA challenges facing future microprocessor design

As microprocessor design progresses from tens of millions of transistors on a chip using 0.18-/spl mu/m process technology to approximately a billion transistors on a chip using 0.10-/spl mu/m and finer process technologies, the microprocessor designer faces unprecedented Electronic Design Automation (EDA) challenges over the future generations of microprocessors. This paper describes the changes in the design environment that will be necessary to develop increasingly complex microprocessors. In particular, the paper describes the current status and the future challenges along three important areas in a design flow: design correctness, performance verification and power management.

DFM: where's the proof of value?

How can design teams employ new tools and develop response methodologies yet still stay within design budgets? How much effort does it require to be an early adopter and what kind of measurable results compensate for this effort? Panelists discuss how their design-for-manufacture (DFM) tools fit into a fixed design methodology, budget and timeline, and give examples of expected ROI (monetary, quality, reduced time-to-market, and comprehensive yield). The aim of this panel is to provide a serious comparison of related DFM technologies on the market and some idea of the cost and difficulty of integrating the tools into a fixed design budget and timeline. Specific results are cited, along with examples of expected ROI (monetary, quality, reduced time-to-market, and comprehensive yield enhancement). The audience should walk away with enough information to make an informed decision on which companies would make sense for their DFM challenges, to reach their own yield and throughput goals

Variation-aware analysis: savior of the nanometer era?

VLSI engineers have traditionally used a variety of CAD analysis tools (e.g. SPICE) to deal with variability. As we go into deep sub micron issues, the analysis is becoming harder due to many secondary effects becoming primary. Panelists will debate the variability trend and present the order of importance of many variability trends (Vdd, Vt, interconnect, Leff, gate width) and their impact on design tools and methodologies. What new design tools, new modeling methodologies, and new (or old) design styles will combine to address variability? Will conservative design to accommodate variability halt the progress of Moores law? Is life as we know it over, or are we facing an opportunity for innovation in tools and design that will move us forward over the barriers that technology has placed in our path?

A case study of two-stage fault location

An industrial implementation of two-stage VLSI fault location is presented. Two-stage fault location was developed to address the size and computation time problems that were making it impractical to automate fault location with fault dictionaries. It does this by reducing the fault list and the test vector set for each faulty chip before dynamically creating a new, small fault dictionary for each diagnosis. The modern fault dictionary and the two-stage fault location technique are explained. For the case study presented, a new Intel chip was chosen. Its test set was developed and fault simulated, and it was prepared for automated fault location. Two-stage fault location was then applied to the fourteen failures available from initial product development production runs. The results are presented.<<ETX>>