Naveed A. Sherwani

Integrated floorplanning and interconnect planning

VLSI fabrication has entered the deep sub-micron era and communication between different components has significantly increased. Interconnect delay has become the dominant factor in total circuit delay. As a result, it is necessary to start interconnect planning as early as possible. We propose a method to combine interconnect planning with floorplanning. Our approach is based on the Wong-Liu (1986) floorplaning algorithm. When the positions, orientations, and shapes of the cells are decided, the pin positions and routing of the interconnects are decided as well. We use a multi-stage simulated annealing approach in which different interconnect planning methods are used in different ranges of temperature to reduce running time. A temperature adjustment scheme is designed to give smooth transitions between different stages of simulated annealing. Experimental results show that our approach performs well.

EDA challenges facing future microprocessor design

As microprocessor design progresses from tens of millions of transistors on a chip using 0.18-/spl mu/m process technology to approximately a billion transistors on a chip using 0.10-/spl mu/m and finer process technologies, the microprocessor designer faces unprecedented Electronic Design Automation (EDA) challenges over the future generations of microprocessors. This paper describes the changes in the design environment that will be necessary to develop increasingly complex microprocessors. In particular, the paper describes the current status and the future challenges along three important areas in a design flow: design correctness, performance verification and power management.

Routing in the Third Dimension

A sliding, radial compression seal is provided between the main gauge casing and a movable blow-out closure element, in a fluid-filled pressure gauge, with yieldable retention of the closure in its normal case closing position. The closure seal insures maintenance of an effective fluig-tight seal of the gauge housing under normal conditions while permitting ready movement of the closure for release of unusual internal pressures.

Integrated floorplanning with buffer/channel insertion for bus-based microprocessor designs

A new approach to the interconnect-driven floorplanning problem that integrates bus planning with floorplanning is presented. The integrated floorplanner is intended for bus-based designs. Each bus consists of a large number of wires. The floorplanner ensures routability by generating the exact location and shape of interconnects (above and between the circuit blocks) and optimizes the timing. Experiments with MCNC benchmarks clearly show the superiority of integrated floorplanning over the classical floorplan-analyze-and-then-re-floorplan approach. Our floorplans are routable, meet all timing constraints, and are on average 12-13% smaller in area as compared to the traditional floorplanning algorithms.

SRC physical design top ten problem

Transistor density on an integrated circuit continues to grow at an exponential rate. The associated complexities when applied to synthesis, layout, and timing analysis will become untenable within the framework of our current technological capabilities. This paper briefly outlines the problems facing the semiconductor industry early into the next decade. A SRC research thrust team consisting of members from various companies prioritized these problems and established a top ten list. This paper includes both problem descriptions as well as metrics to benchmark proposed solutions.

On the use of flexible, rectilinear blocks to obtain minimum-area floorplans in mixed block and cell designs

This paper presents three minimum-area floorplanning algorithms that use flexible arbitrary rectilinear shapes for the standard cell regions in MBC design. The first algorithm (pure HCST) introduces a grid traversal technique which guarantees a minimum-area floorplan. The second algorithm (Hybrid-BF) uses a combination of HCST and Breadth First (BF) traversals to give a practical solution that approximately places flexible blocks at specified locations called seeds. The third algorithm (Hybrid-MBF) improves on the shapes of the flexible blocks generated by Hybrid-BF by using a combination of HCST and a Modified Breadth First (MBF) traversal. All three algorithms are polynomial in the number of grid squares. Optimized implementations of Hybrid-BF and Hybrid-MBF required less than two seconds on a SUN SPARCstation 10.

Distance in stratified graphs

AbstractA graph G is stratified if its vertex set is partitioned into classes, called strata. If there are k strata, then G is k-stratified. These graphs were introduced to study problems in VLSI design. The strata in a stratified graph are also referred to as color classes. For a color X in a stratified graph G, the X-eccentricity eX(v) of a vertex v of G is the distance between v and an X-colored vertex furthest from v. The minimum X-eccentricity among the vertices of G is the X-radius radXG of G and the maximum X-eccentricity is the X-diameter diamXG. It is shown that for every three positive integers a, b and k with a≤b, there exist a k-stratified graph G with radXG = a and diamXG = b. The number sX denotes the minimum X-eccetricity among the X-colored vertices of G. It is shown that for every integer t with radXG ≤ t ≤ diamXG, there exist at least one vertex v with eX(v) = t; while if radXG ≤ t ≤ sX, then there are at least two such vertices. The X-center CX(G) is the subgraph induced by those vertices v with eX(v) = radXG and the X-periphery PX (G) is the subgraph induced by those vertices v with eX(G) = diamXG. It is shown that for k-stratified graphs H1, H2,..., Hk with colors X1, X2,..., Xk and a positive integer n, there exists a k-stratified graph G such that CXi(G)≅ Hi (1 ≤; i≤; k1) and n

Optimal algorithms for planar over-the-cell routing problems

d(C_{x_i } (G),C_{x_j } (G)) geqslant n{text{ for }}i ne j.