Shiyuan Zheng

A 21–48 GHz Subharmonic Injection-Locked Fractional-N Frequency Synthesizer for Multiband Point-to-Point Backhaul Communications

This paper presents a mm-wave subharmonic injection-locked (SHIL) fractional-N frequency synthesizer for wireless multiband point-to-point backhaul communications. The SHIL synthesizer implements a low-phase-noise 4.5-6.1 GHz PLL and injects its output to a ÷3/÷4 dual-modulus divider followed by an ultra-wideband injection-locked frequency-multiplier (ILFM) chain to achieve excellent phase noise over an ultra-wide frequency tuning range. The proposed ILFM chain employs higher-order LC tanks to generate a rippled phase response around 0 ° over a wide frequency range to significantly enhance the locking range and to eliminate expensive mm-wave frequency calibration loops. Fabricated in a 65 nm CMOS process, the synthesizer prototype measures a continuous output frequency range from 20.6 to 48.2 GHz with frequency resolution of 220 kHz and output phase noise between -107.0 and -113.9 dBc/Hz at 1 MHz offset while consuming 148 mW and occupying 1850 × 1130 μm 2.

A CMOS WCDMA/WLAN Digital Polar Transmitter With AM Replica Feedback Linearization

This paper presents a 65 nm CMOS digital polar transmitter with on-chip power amplifier (PA) for WCDMA and WLAN application. The proposed architecture is composed of a digital interpolation filter for up-sampling of the input amplitude-control word (ACW), a 9-bit switched-capacitor array for the digital polar modulation (DPM), and a 6-bit PA array to achieve the output power range for the target applications. A linearization technique is implemented by adaptively changing the PA bias voltage according to the RF envelope. To generate this bias voltage, the RF envelope of the PA input is extracted by a digital-to-analog converter (DAC) with the ACW signals as its input. A scaled replica of the PA, which only needs to operate at the Amplitude Modulation (AM) frequency, is employed to sense the RF envelope and to regulate the PA bias voltage with an analog feedback loop to minimize the distortion in the AM path. Even without amplitude pre-distortion, the transmitter system measures RMS-EVM of 2.83% and 4.07% for WCDMA and WLAN 54-Mb/s 64-QAM OFDM respectively while providing a peak output power of 20.4 dBm with PAE 32.3%.

A WCDMA/WLAN Digital Polar Transmitter With Low-Noise ADPLL, Wideband PM/AM Modulator, and Linearized PA

This paper presents a single-chip digital-intensive polar transmitter for WCDMA and WLAN integrating a low-phase-noise all-digital phase-locked loop (ADPLL), a digitally-controlled wideband phase/amplitude modulator, and a calibration-free high-linearity power amplifier. From the ADPLL, the 1.7-2.5 GHz LO signal is generated together with a ÷1.5 frequency divider to eliminate DCO pulling. The phase noise of the ADPLL is optimized by using a linearized stochastic TDC with 3 ps resolution and a Class-C quadrature DCO (QDCO) with embedded quadrature phase shifter and quantization-noise filter. A 2-segment ΣΔ switching phase modulator enhances the PM bandwidth up to 200 MHz, and a digital polar amplifier employs AM-replica linearization to eliminate AM pre-distortion. The TX achieves a -1 dB output compression point of 22.8 dBm with an overall system efficiency of 27.6% and measures EVM of 4% for a 20 MHz 64-QAM signal at an output power of 13.8 dBm.

A 4.1-to-6.5GHz transformer-coupled CMOS quadrature digitally-controlled oscillator with quantization noise suppression

A wideband quadrature digitally-controlled oscillator (QDCO) operates in Class-C mode with embedded phase shifters for better phase noise and I-Q accuracy. Transformer-coupled fine tuning capacitors are controlled by a ΣΔ modulator with embedded filter to achieve fractional quantization step with intrinsic out-band noise suppression. The QDCO fabricated in 65nm CMOS measures tuning range of 45% from 4.1GHz to 6.5GHz with frequency resolution of 5Hz while achieving 1.2° phase error and a phase noise of -145.3dBc/Hz at 10MHz. It consumes 15mA from a 1.2V supply corresponding to a FoM of 186.6dBc/Hz and a FoMT of 199.8dBc/Hz.

A 0.9GHz–5.8GHz SDR receiver front-end with transformer-based current-gain boosting and 81-dB 3rd-order-harmonic rejection ratio

A 0.9GHz-to-5.8GHz SDR RFE is presented employing a dual-band LNA with a switchable 3-coil transformer as loading for current-gain boosting and an automatic LO phase-error detection and calibration circuitry for harmonic rejection. Fabricated in 65nm CMOS and integrated with a fully-integrated all-digital synthesizer (ADFS), the RFE measures NF between 2.9dB and 3.8dB, IIP3 between -1.6dBm and -12.8dBm, 3rd-order HRR of 81dB, and 5th-order HRR of 70dB, while consuming between 66mA and 82mA from a 1.2V and occupying a total chip area of 4.2 mm2.

A CMOS 21-48GHz fractional-N synthesizer employing ultra-wideband injection-locked frequency multipliers

Higher-order LC tanks with proper design parameters are proposed to widen the phase response to enhance the frequency locking range of mm-Wave injection-locked frequency multipliers (ILFMs). Employing a chain of such ILFMs at the output, a complete ultra-wideband fractional-N frequency synthesizer is demonstrated. Fabricated using a 65nm CMOS process, the synthesizer prototype measures a continuous output frequency tuning range of 80.2% from 20.6GHz to 48.2GHz when locked to a 4.5GHz to 6.1GHz fractional-N PLL with excellent phase noise <; -107dBc/Hz at 1MHz offset while consuming 148 mW.

A WCDMA/WLAN digital polar transmitter with AM replica feedback linearization in 65nm CMOS

A 65nm CMOS digital polar transmitter for WCDMA and WLAN is presented, which consists of a 9bit digitally-controlled switch-capacitor polar modulator and a 6-bit power amplifier array with a proposed linearity-enhancement technique. Even without AM-AM pre-distortion, the transmitter system measures RMS-EVM of 2.83% and 4.07% for WCDMA and WLAN 54-Mb/s OFDM, respectively; while providing a peak output power of 20.4dBm with PAE 32.3%.

A 0.9–5.8-GHz Software-Defined Receiver RF Front-End With Transformer-Based Current-Gain Boosting and Harmonic Rejection Calibration

A 0.9–5.8-GHz receiver RF front-end (RFE) integrating a dual-band low-noise transconductance amplifier (LNTA), a passive harmonic-rejection (HR) down-conversion mixer, and an all-digital frequency synthesizer for software-defined radios are presented. A switchable three-coil transformer acting as the interface between the LNTA and the mixer features current-gain boosting in addition to wideband operation. Automatic local oscillator phase-error detection and calibration circuitry is implemented for the mixers to achieve high HR ratio (HRR). Fabricated in 65-nm CMOS, the RFE measures the noise figure between 2.9 and 3.8 dB, the third-order input intercept point (IIP3) between −1.6 and −12.8 dBm, the third-order HRR of 81 dB, and the fifth-order HRR of 70 dB, while consuming 66–82 mA from a 1.2-V supply and occupying a chip area of 4.2 mm2.

A WCDMA/WLAN digital polar transmitter with low-noise ADPLL, wide-band PM/AM modulator and linearized PA in 65nm CMOS

A single-chip digital polar transmitter integrates an all-digital synthesizer, a PM/AM modulator, and a linearized power amplifier for WCDMA/WLAN. The 1.7~2.5GHz LO signal is generated from an ADPLL together with a ÷1.5 divider to eliminate DCO pulling. A 2-segment ΣΔ phase modulator enhances the PM bandwidth up to 200MHz, and a digital polar amplifier employs AM-replica linearization to eliminate predistortion. The TX measures EVM 4% for a 20MHz-bandwidth 64-QAM while providing a peak output power of 22.1dBm with bit-to-RF efficiency 27.6%.

A 4.1GHz-6.5GHz all-digital frequency synthesizer with a 2 nd -order noise-shaping TDC and a transformer-coupled QVCO

A 4.1GHz-6.5GHz all-digital fractional-n frequency synthesizer is presented employing a 2nd-order noise-shaping time-to-digital converter (TDC) and an embedded-FIR-filter transformer-coupled quadrature digitally-control oscillator (QDCO). Implemented in a 65nm CMOS, the prototype measures phase noise of -100dBc/Hz in-band and -145dBc/Hz at 20MHz offset from a 4.5GHz carrier while consuming 26mW from 1.2V supply and occupying 1mm2. The IQ phase error is smaller than 1.2°