Alan W. L. Ng

A 1-V 17-GHz 5-mW CMOS Quadrature VCO Based on Transformer Coupling

A 1-V 17-GHz 5-mW quadrature voltage-controlled oscillator (QVCO) based on transformer coupling is presented. Transformer coupling between two LC tank oscillators is proposed to achieve quadrature outputs with improved performance in terms of high frequency, wide tuning range, low phase noise, and low power as compared to existing active-coupling QVCOs. Implemented in a 0.18-mum CMOS process, the proposed QVCO measures a frequency tuning range of 16.5% at 17 GHz and phase noise of -110 dBc/Hz at 1 MHz offset while consuming 5 mA from a 1-V power supply and occupying a core area of 0.37 mm2.

A 1-V 24-GHz 17.5-mW phase-locked loop in a 0.18-/spl mu/m CMOS process

A 1-V 24-GHz 17.5-mW fully integrated phase-locked loop employing a transformer-feedback voltage-controlled oscillator and a stacked divide-by-2 frequency divider for low voltage and low power is presented. Implemented in a 0.18-/spl mu/m CMOS process and operated at 24 GHz with a 1-V supply, the PLL measures in-band phase noise of -106.3 dBc at a frequency offset of 100 kHz and out-of-band phase noise of -119.1 dBc/Hz at a frequency offset of 10 MHz. The PLL dissipates 17.5 mW and occupies a core area of 0.55 mm/sup 2/.

A 1-V 86-mW-RX 53-mW-TX Single-Chip CMOS Transceiver for WLAN IEEE 802.11a

A 1-V WLAN IEEE 802.11a CMOS transceiver integrates all building blocks on a single chip including a transformer-feedback VCO and a stacked divider for the frequency synthesizer and 8-bit IQ ADCs and 8-bit IQ DACs. Fabricated in a 0.18-mum CMOS process and operated at a single 1-V supply, the receiver and the transmitter consume 85.7 mW and 53.2 mW, including the frequency synthesizer, respectively. The total chip area with pads is 12.5 mm2.

A 1V 17GHz 5mW Quandrature CMOS VCO based on transformer coupling

A 1V 17GHz 5mW QVCO is designed using transformer coupling for high frequency, low voltage and low phase noise. Implemented in 0.18mum CMOS, the 0.37mm2 chip achieves a tuning range of 16.5% at 17GHz, a phase noise of -110dBc/Hz at 1MHz offset while using 5mA from a 1V supply, resulting in a FOM of 187.6dB

0.9mW 7GHz and 1.6mW 60GHz frequency dividers with locking-range enhancement in 0.13µm CMOS

Frequency dividers are key components for frequency synthesis in wireless and wireline communication systems. Among different types of frequency dividers, LC-based injection-locked frequency dividers (ILFDs) feature high-frequency operation at low power consumption, but their locking range is quite narrow due to the high-Q nature of the resonator. Recently, design techniques to enhance the locking range of ILFDs have been reported. Injection into two coupled LC oscillators [1] and sandwiched injection into two identical LC oscillators [2] are proposed, but these techniques are suitable for dividers with quadrature outputs. Inductive-peaking and transconductance enhancement techniques [3, 5] are also used but they require extra inductors and thus larger chip area. In this paper, a simple but effective technique is presented to improve the locking range of ILFDs without extra inductive components while consuming low power.

A 1V 24GHz 17.5mW PLL in 0.18/spl mu/m CMOS

A 1V 24GHz fully integrated PLL is designed in a 0.18/spl mu/m. CMOS process using a transformer-feedback VCO and a stacked frequency divider. The PLL measures an in-band phase noise of -106.3dBc/Hz at 100kHz offset and an out-of-band phase noise of -119.1dBc/Hz at 10MHz offset. It consumes 17.5mW from a 1V supply and occupying an area of 0.55mm/sup 2/.

A 24-GHz and 60-GHz dual-band standing-wave VCO in 0.13µm CMOS process

By exploiting the intrinsic multiple oscillation modes of a standing-wave oscillator, a dual-band millimeter-wave VCO is designed. Implemented in 0.13µm CMOS with an area of 0.05mm2, the VCO prototype measures a dual-band operation at 24 GHz and 60 GHz with tuning range of 10.8% and 7.2%, phase noise of −120dBc/Hz and −114dBc/Hz at 10MHz offset, power consumption of 11mW and 24mW, corresponding to FoM of −177dB and −176dB, respectively.

A 1V Low-Power Single-Chip CMOS WLAN IEEE 802.11a Transceiver

A 1V WLAN IEEE 802.11a CMOS transceiver integrates all building blocks on a single chip including a transformer-feedback VCO and a stacked divider for the synthesizer and 8-bit IQ ADCs and 8-bit IQ DACs. Fabricated in a 0.18-mum CMOS process and operated at a single 1-V supply, the receiver and the transmitter consume 85.7mW and 53.2mW, including the frequency synthesizer, respectively. The total chip area with pads is 12.5 mm2

A 0.9GHz–5.8GHz SDR receiver front-end with transformer-based current-gain boosting and 81-dB 3rd-order-harmonic rejection ratio

A 0.9GHz-to-5.8GHz SDR RFE is presented employing a dual-band LNA with a switchable 3-coil transformer as loading for current-gain boosting and an automatic LO phase-error detection and calibration circuitry for harmonic rejection. Fabricated in 65nm CMOS and integrated with a fully-integrated all-digital synthesizer (ADFS), the RFE measures NF between 2.9dB and 3.8dB, IIP3 between -1.6dBm and -12.8dBm, 3rd-order HRR of 81dB, and 5th-order HRR of 70dB, while consuming between 66mA and 82mA from a 1.2V and occupying a total chip area of 4.2 mm2.

Transformer-based current-gain-boost technique for dual-band and wide-band receiver front-ends

Dual-band and wide-band receiver-front-ends (RFEs) using transformer-based current-gain-boost techniques are designed in 0.13μm CMOS. With a single switchable 3-coil transformer, the first dual-band RFE prototype measures NF of 2.5dB and 3.5dB and voltage gain of 20.7dB and 17dB at 1.7GHz and 3.8GHz, respectively. The second wide-band RFE achieves 0dBm IIP3 with 4dB NF and 13dB voltage gain over a frequency range from 2GHz to 5GHz.