Sho Yamamoto
Hitachi
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Publication
Featured researches published by Sho Yamamoto.
international solid-state circuits conference | 1985
Sho Yamamoto; Kiyofumi Uchibori; Kouichi Nagasawa; Satoshi Meguro; Tokumasa Yasui; Osamu Minato; T. Masuhara
A 45ns 256K (32K×8b) CMOS SRAM with a 200mW at 10MHz active power dissipation will be described. The RAM utilizes variable impedance data-line loads, pulsed word lines and latched output buffers. A polycide vss-line is used in a 95μm2memory cell.
Archive | 1986
Shuji Ikeda; Satoshi Meguro; Kotaro Nishimura; Sho Yamamoto; Nobuyoshi Tanimura
Archive | 1988
Shuji Ikeda; Kouichi Nagasawa; Satoshi Meguro; Sho Yamamoto
Archive | 1988
Sho Yamamoto; Osamu Minato; Makoto Saeki; Yasuo Yoshitomi; Hideaki Nakamura; Masaaki Kubotera
Archive | 1982
Nobuyoshi Tanimura; Sho Yamamoto; Kazuo Yoshizaki; Isao Akima
Microelectronics Reliability | 1991
Shuji Ikeda; Kouich Nagasawa; Satoshi Meguro; Sho Yamamoto
Archive | 1985
Shuji Ikeda; Kouichi Nagasawa; Satoshi Meguro; Sho Yamamoto
Archive | 1985
Sho Yamamoto; Osamu Minato; Makoto Saeki; Yasuo Yoshitomi; Hideaki Nakamura; Masaaki Kubotera
Archive | 1985
Shuji Ikeda; Kouichi Nagasawa; Satoshi Meguro; Sho Yamamoto
international solid-state circuits conference | 1984
Sho Yamamoto; Kiyofumi Uchibori; Kouichi Nagasawa; Satoshi Meguro; Tokumasa Yasui; Osamu Minato; Toshiaki Masuhara; William H. Herndon
