Shohei Hayashi

Formation of High Crystallinity Silicon Films by High Speed Scanning of Melting Region Formed by Atmospheric Pressure DC Arc Discharge Micro-Thermal-Plasma-Jet and Its Application to Thin Film Transistor Fabrication

Lateral grain with a maximum grain size of ~60 µm was grown by high speed scanning of a molten region in amorphous Si (a-Si) films formed by micro-thermal-plasma-jet irradiation. The a-Si transformed into crystalline through solid phase crystallization, followed by melting and recrystallization induced by the movement of molten region. The laterally crystallized Si films show a high crystalline volume fraction of ~100%. Thin film transistors were fabricated using Si films formed by high-speed (4000 mm/s) lateral crystallization, and a very high field effect mobility of 350 cm2 V-1 s-1 was successfully obtained.

Direct observation of grain growth from molten silicon formed by micro-thermal-plasma-jet irradiation

Phase transformation of amorphous-silicon during millisecond annealing using micro-thermal-plasma-jet irradiation was directly observed using a high-speed camera with microsecond time resolution. An oval-shaped molten-silicon region adjacent to the solid phase crystallization region was clearly observed, followed by lateral large grain growth perpendicular to a liquid-solid interface. Furthermore, leading wave crystallization (LWC), which showed intermittent explosive crystallization, was discovered in front of the moving molten region. The growth mechanism of LWC has been investigated on the basis of numerical simulation implementing explosive movement of a thin liquid layer driven by released latent heat diffusion in a lateral direction.

Application of Thermal Plasma Jet Irradiation to Crystallization and Gate Insulator Improvement for High-Performance Thin-Film Transistor Fabrication

Large grains with a maximum length of ~60 µm were grown by high speed scanning (~4000 mm/s) of a molten region in amorphous silicon (a-Si) films formed by micro-thermal-plasma-jet (µ-TPJ) irradiation. By reducing the TPJ nozzle diameter and increasing the spacing between anode and cathode, the power density transferred to a-Si film surface increased to as high as 53 kW/cm2, which enabled melting and lateral solidification in the microsecond time domain. The a-Si transformed to crystalline through solid-phase crystallization, followed by melting and recrystallization induced by the movement of the molten region with the maximum size of ~483 µm in width and ~990 µm in length. The laterally crystallized Si films show anisotropic large grains and a high crystalline volume fraction of ~100% and preferential surface orientation of (111) plane. Thin-film transistors (TFTs) fabricated by solid-phase-crystallized microcrystalline Si (µc-Si) show a small field effect mobility (µFE) of ~2 cm2 V-1 s-1 with small variation less than 1%, while the high-speed lateral-crystallization (HSLC) Si film shows a very high µFE of 350 cm2 V-1 s-1. We improved the bulk bond network of the low-temperature-deposited gate SiO2 films by TPJ-induced millisecond annealing. By combining TPJ annealing and postmetallization annealing (PMA), a high-quality SiO2/Si interface with a density of interface states (Dit) of 3.0 ×1010 cm-2 eV-1 is obtained. In addition, we found that the improvement in the bulk bond network of SiO2 is quite effective to improve the stress immunity of µc-Si TFTs. TFTs fabricated with TPJ-annealed gate SiO2 films show much smaller on-current degradation and threshold voltage shift after DC bias stress compared with untreated TFTs. Not only the threshold voltage (Vth) shift under high-gate-field stress condition, but also on-current degradation under drain avalanche hot carrier (DAHC) generation condition are markedly suppressed. This improvement is attributed to the reduction of Si–OH bonds and relaxation of the bulk chemical bond network of SiO2 induced by TPJ annealing.

Layer Transfer and Simultaneous Crystallization Technique for Amorphous Si Films with Midair Structure Induced by Near-Infrared Semiconductor Diode Laser Irradiation and Its Application to Thin-Film Transistor Fabrication

A novel layer transfer and simultaneous crystallization of amorphous silicon (a-Si) films induced by near-infrared semiconductor-diode-laser (SDL) irradiation has been investigated. The a-Si films supported by narrow quartz columns on a starting quartz substrate and a counter substrate [glass and poly(ethylene terephthalate)] were in face-to-face contact, and an SDL irradiated the a-Si films with midair structure. After SDL irradiation, the Si films were completely transferred and crystallized simultaneously on the counter substrates. In-situ monitoring revealed that the layer transfer took place either in the solid phase or the liquid phase followed by phase transformation in the cooling period. High performance polycrystalline Si thin-film transistors were successfully fabricated on the transferred Si films, which showed a high on/off ratio of more than 105 and a field-effect mobility as high as 268 cm2 V-1 s-1.

Properties of Al Ohmic Contacts to n-type 4H-SiC Employing a Phosphorus-Doped and Crystallized Amorphous-Silicon Interlayer

Contact property of aluminum and 4H-SiC wafer with crystallized amorphous-silicon (a-Si) interlayer was investigated. A phosphorus-doped a-Si layer on SiC wafer was crystallized by annealing at 1377 °C. Good ohmic contact behavior and contact resistivity of 2.1 × 10-6 Ωcm2 were obtained without silicidation annealing process. Furthermore, non-doped crystallized a-Si layer insertion layer also showed ohmic contact property. However, high contact resistivity of 8.2×10-4 Ωcm2 was obtained in the non-doped a-Si sample. X-ray photo-electron spectroscopy analysis suggests that conduction band offset is significantly reduced between crystallized a-Si and SiC wafer. Therefore, a-Si insertion layer is effective for Schottky barrier height decreasing and high doping into Si layer forms low contact resistivity between Al and SiC, indirectly.

Improvement in Characteristic Variability of TFTs Using Grain Growth Control by Micro Thermal Plasma Jet Irradiation on a-Si Strips

Grain growth from molten silicon during micro-thermal-plasma-jet ( μ-TPJ) irradiation has been controlled by applying amorphous-silicon (a-Si) strips. The grain boundaries (GBs) in strip pattern with the width of 1 μm are significantly reduced compared with the case without strip pattern. In strip pattern, random GBs were almost excluded and most of the strips consist of Σ3 coincidence site lattices (CSLs) GBs or in some cases single grains. TFTs with strip pattern showed threshold voltage (V_th), field effect mobility (μ_FE) and sub-threshold swing value (S) of 1.8 ±0.10 V, 303 ±24 cm²/V·s and 240±17 mV/dec, respectively. In the case of P-type TFTs, they were -1.8±0.22 V, 98±7 cm²/V·s, 285 ±17 mV/dec, respectively. TFTs fabricated with the proposed pattern showed high performance and the variability reduced to 1/3 compared with the case without strip pattern. These characteristics and small variation with proposed patterns enabled us to operate CMOS circuits. The 8-bits shift register fabricated with proposed pattern was operated at a supply voltage of 5 V clock frequency of 4 MHz.

Fabrication of High-Performance Thin-Film Transistors on Glass Substrate by Atmospheric Pressure Micro-Thermal-Plasma-Jet-Induced Lateral Crystallization Technique

Amorphous silicon (a-Si) films deposited by plasma-enhanced chemical vapor deposition (PECVD) were patterned to strips with a width ranging from 1 to 50 µm, and irradiated with an atmospheric pressure micro-thermal-plasma-jet (µ-TPJ) to induce high-speed lateral crystallization (HSLC). From electron backscattering diffraction patterns (EBSPs), the growth of ~20-µm-long single grains was observed in a narrow line of 1 µm width under a µ-TPJ scan speed as high as 4000 mm/s. TFTs with a large channel length (L)/width (W) of 40 µm/50 µm show a field-effect mobility (µFE) of 284 cm2 V-1 s-1, whereas decreasing W monotonically increased µFE to 477 cm2 V-1 s-1 at W = 2 µm. By applying µ-TPJ to strip a-Si films, we can form single-crystalline Si at predetermined positions and obtain TFTs with reasonably high performance. We confirmed that HSLC is applicable to a-Si films on conventional glass substrates without crack generation by either inserting a buffer layer underneath a-Si films, or heating the samples during µ-TPJ irradiation. A new positioning method using a Si slit mask is also demonstrated. TFTs fabricated on glass with a buffer layer inserted underneath the a-Si films show a high µFE of 267 cm2 V-1 s-1.

Leading Wave Crystallization Induced by Micro-Thermal-Plasma-Jet Irradiation of Amorphous Silicon Films

The crystalline grain growth of silicon induced by micro-thermal-plasma-jet irradiation has been directly observed using a high-speed camera. An oval-shaped molten region (MR) was formed after the solid phase crystallization (SPC), and it was clearly observed that laterally large grains grew perpendicular to the liquid–solid interface. Leading wave crystallization (LWC), which showed intermittent grain growth with a liquid–solid interface velocity as high as 4500 mm/s, was discovered in between the MR and SPC region. From numerical calculation, it has been clarified that the explosive lateral growth of LWC is triggered by the formation of a thin liquid layer and the explosive propagation of the layer is driven by released latent heat.

Estimation of Phosphorus-Implanted 4H-SiC Layer Recrystallization by Electron-Back-Scattering Diffraction Pattern Analysis

Image quality (IQ) values of an electron-back-scattering diffraction (EBSD) pattern were used to investigate layer recrystallization for the phosphorus-implanted 4H SiC. We prepared a slope-structured amorphous Si on a Si substrate sample to simulate the recrystallization model of the ion-implanted layer after activation annealing. Phosphorus-implanted and recrystallize-annealed Si and SiC samples were also investigated and the Kikuchi-pattern obscuration was observed for a thicker a-Si layer on the slope-structured sample. The IQ values also decreased. Our results show that ion-implantation damage recovery can be estimated by the EBSD pattern analysis. IQ value variation is in good agreement with the sheet resistance changing with the annealing temperature. The IQ values obtained from the EBSD measurements can be used for crystalline recovery estimation on impurity-implanted SiC layer in a nanoscale resolution.

Grain growth induced by micro-thermal-plasma-jet irradiation to narrow amorphous silicon strips

Amorphous silicon (a-Si) strips were crystallized by micro-thermal-plasma-jet (μ-TPJ) irradiation. The formation of random grain boundaries (GBs) induced by the collision of liquid-solid interfaces was observed by using a high-speed camera. When Si strip thickness (tSi) was 50 nm, total GB length significantly decreased with the decrease in strip width (W) from 2 to 1 μm, especially random GBs decreased with the decrease in W. Total and low angle GB length were decreased in the thicker Si strips of tSi = 100 and 200 nm, and electrically active GBs such as random and Σ9 crystal site lattice hardly formed in all W. The grains longer than 50 μm had the tendency to face to {111} at surface direction, {110} at strip width direction, and {100} at strip length direction. These long growth grains rotated very slowly to growth direction, and the rotation axis was strip width direction. The maximum growth length was 977 μm, and the grain showed very small crystal plane rotation of 0.032 degrees/μm.