Shoichi Hara

A 9.3MHz to 5.7GHz tunable LC-based VCO using a divide-by-N injection-locked frequency divider

This paper proposes a novel wideband voltage-controlled oscillator (VCO) for multi-band transceivers. The proposed oscillator has a core VCO and a tuning-range extension circuit, which consists of an injection-locked frequency divider (ILFD), and flip flop dividers. The 2-stage differential ILFD can generate quadrature outputs, and it realizes 2, 3, 4, and 6 of divide ratio with very wide output frequency range. The proposed circuit is implemented by using a 90nm CMOS process, and the chip area is 250μm × 200 μm. The measured results achieves 9.3 MHz-to-5.7 GHz (199%) of continuous frequency tuning range with −210 dBc/Hz of FoMT.

10MHz to 7GHz quadrature signal generation using a divide-by-4/3, -3/2, -5/3, -2, -5/2, -3, -4, and -5 injection-locked frequency divider

This paper presents a wideband LC-based VCO using a divide-by-fractional-N injection-locked frequency divider (ILFD), and the fractional-N division is realized by the proposed modulated injection technique. The feedback modulation of incident signals eliminates unwanted injections, which contributes to enlarge the locking range. The ILFD consists of a 2-stage differential ring oscillator, which achieves the multi-decade frequency tuning with quadrature outputs. The proposed circuit is implemented by using a 90 nm CMOS process, and the measured results achieves 10 MHz-to-7 GHz of continuous frequency tuning range with 9.6–15.6mW of power consumption. The chip area is 250 × 200 µm2.

A Compact and Low-Power Fractionally Injection-Locked Quadrature Frequency Synthesizer Using a Self-Synchronized Gating Injection Technique for Software-Defined Radios

This paper describes a compact and low-power frequency synthesizer with quadrature phase output for software-defined radios (SDRs). The proposed synthesizer is constructed using a core phase-locked loop (PLL), which is coupled with a fractional-N injection-locked frequency divider (ILFD). The fractional-N injection-locking operation is achieved by the proposed self-synchronized gating injection technique. The principle of a fractional-N injection locking operation and the concept of the proposed circuits are described in detail. Analysis for predicting the locking range of the proposed fractional-N ILFD is investigated. A digital calibration scheme is adopted in order to compensate for process, voltage, and temperature (PVT) variations. Implemented in a 65 nm CMOS process, this work demonstrates continuous frequency coverage from 10 MHz to 6.6 GHz with quadrature phase output while occupying a small area of 0.38 mm2 and consuming 16 to 26 mW, depending on the output frequency. The normalized phase noise achieves -135.3 dBc/Hz at an offset of 3 MHz and -95.1 dBc/Hz at an offset of 10 kHz, both from a carrier frequency of 1.7 GHz.

Design optimization of voltage controlled oscillators in consideration of parasitic capacitance

This paper presents a study of design optimization of voltage-controlled oscillators. The phase noise of LC-type oscillators is basically limited by quality factor of inductors. It is experimentally known that higher-Q inductors can be achieved at higher frequencies while oscillation frequency is limited by parasitic capacitances. In this paper, the minimum transistor size and degradation of quality factor caused by the switched-capacitor array are analytically estimated, and the maximum oscillation frequency of VCOs is also derived from the equivalent circuit considering parasitic capacitances. According to the analytical evaluation, the phase noise of VCO using 65-nm CMOS is 2 dBc/Hz better than that of 180-nm CMOS.

Design space exploration of low-phase-noise LC-VCO using multiple-divide technique

This paper proposes a multiple-divide technique using by-2, by-3, and by-4 frequency dividers to realize a lower phase-noise LC-VCO, and explores the design space of low-phase-noise VCO using the multiple-divide technique. In the simulated results using 90-nm CMOS model parameters, the optimum frequency range, achieving better than -191dBc/Hz of FoM, can be extended from 6-12 GHz to 1.5-12 GHz.

60 GHz injection locked frequency quadrupler with quadrature outputs in 65 nm CMOS process

This paper presents a LC-based sub-harmonic injection-locked frequency quadrupler which multiplies a 15 GHz input to 60 GHz quadrature(I/Q) output signals. The proposed quadrupler can use a lower-frequency PLL for incident signal than doublers and triplers, which is very advantageous to implement a wide-tuning and low-phase-noise PLL. The proposed frequency quadrupler is implemented by using a 65nm CMOS process. It consumes 5.9mW with a 0.6V supply voltage, and the core layout area is 160 µm × 110 µm.