Rui Murakami

A 60-GHz 16QAM/8PSK/QPSK/BPSK Direct-Conversion Transceiver for IEEE802.15.3c

This paper presents a 60-GHz direct-conversion transceiver using 60-GHz quadrature oscillators. The transceiver has been fabricated in a standard 65-nm CMOS process. It in cludes a receiver with a 17.3-dB conversion gain and less than 8.0-dB noise figure, a transmitter with a 18.3-dB conversion gain, a 9.5-dBm output 1 dB compression point, a 10.9-dBm saturation output power and 8.8-% power added efficiency. The 60-GHz frequency synthesizer is implemented by a combination of a 20-GHz PLL and a 60-GHz quadrature injection-locked oscillator, which achieves a phase noise of -95 dBc/Hz@l MHz-offset at 60 GHz. The transceiver realizes IEEE802.15.3c full-rate wireless communication for all 16QAM/8PSK/QPSK/BPSK modes, and the communication distances with the full data rate using 2.16-GHz bandwidth, measured with an antenna built in the package, are 2.7-m (BPSK/QPSK) and 0.2-m (8PSK/16QAM). The measured maximum data rates are 8 Gb/s in QPSK mode and 11 Gb/s in 16QAM mode over a 5 cm wireless link within a bit error rate (BER) of <;10-3. The transceiver consumes 186 mW from a 1.2-V supply voltage while transmitting and 106 mW from 1.0-V supply voltage while receiving. Both transmitter and receiver are driven by a 20-GHz PLL, which consumes 66 mW, including output buffer, from a 1.2-V supply voltage.

Full Four-Channel 6.3-Gb/s 60-GHz CMOS Transceiver With Low-Power Analog and Digital Baseband Circuitry

This paper presents a 60-GHz direct-conversion RF front-end and baseband transceiver including analog and digital circuitry for PHY functions. The 65-nm CMOS front-end consumes 319 and 223 mW in transmitting and receiving mode, respectively. It is capable of more than 7-Gb/s 16QAM wireless communication for every channel of the 60-GHz standards, which can be extended up to 10 Gb/s. The 40-nm CMOS baseband including analog, digital, and I/O consumes 196 and 427 mW for 16QAM in transmitting and receiving modes, respectively. In the analog baseband, a 5-b 2304-MS/s ADC consumes 12 mW, and a 6-b 3456-MS/s DAC consumes 11 mW. In the digital baseband integrating all PHY functions, a (1440, 1344) LDPC decoder consumes 74 mW with the low energy efficiency of 11.8 pJ/b. The entire system including both RF and BB using a 6-dBi antenna built in the organic package can transmit 3.1 Gb/s over 1.8 m in QPSK and 6.3 Gb/s over 0.05 m in 16QAM.

A Low Phase Noise Quadrature Injection Locked Frequency Synthesizer for MM-Wave Applications

This paper proposes a 60 GHz quadrature PLL frequency synthesizer for the IEEE802.15.3c with wide tuning range and low phase noise. The synthesizer is constructed using a 20 GHz PLL that is coupled with a Quadrature Injection Locked Oscillator (QILO) as a frequency tripler to generate the 60 GHz signal. The 20 GHz PLL generates a signal with a phase noise that is lower than -105 dBc/Hz using tail feedback to improve the phase noise while having a 17% tuning range. The proposed 60 GHz QILO uses a combination of parallel and tail injection to enhance the locking range by improving the QILO injection efficiency at the moment of injection and has a 12% tuning range. Both the 20 GHz PLL and the QILO were fabricated as separate chips using a 65 nm CMOS process and measurement results show a phase noise that is less than -95 dBc/Hz@1 MHz at 60 GHz while consuming 80 mW from a 1.2 V supply. To the authors knowledge this phase noise is about 20 dB better than recently reported QPLLs and about 10 dB compared to differential PLLs operating at a similar frequency and at a similar offset.

A full 4-channel 6.3Gb/s 60GHz direct-conversion transceiver with low-power analog and digital baseband circuitry

This paper presents a 60 GHz direct-conversion front-end and baseband transceiver, including analog and digital circuitry for the PHY functions. The 65 nm CMOS front-end consumes 319 mW and 223 mW in transmitting and receiving mode, respectively, and is capable of more than 7 Gb/s 16QAM wireless communication for every channel of the 60 GHz standards. The 40 nm CMOS baseband incorporating LDPC consumes 196 mW and 398 mW for 16QAM in transmitting and receiving mode, respectively. The entire system, using a 6dBi antenna built in an organic package, can transmit 3.1Gb/s over 1.8 m in QPSK and 6.3 Gb/s over 0.05 m in 16QAM.

A 58–63.6GHz quadrature PLL frequency synthesizer in 65nm CMOS

This paper proposes a 60GHz quadrature PLL frequency synthesizer that has a tuning range capable of covering the whole band specified by the IEEE802.15.3c with exceptional phase noise. The synthesizer is constructed using a 20GHz PLL that is coupled with a frequency tripler to generate the 60GHz signal. The 20GHz PLL generates a signal with a phase noise as low as −106dBc/Hz using tail feedback to improve the phase noise. The proposed 60GHz ILO uses a combination of parallel and tail injection to enhance the locking range by reducing the Injection Locked Oscillator (ILO) current at the moment of injection. Both the 20GHz PLL and the ILO were fabricated using a 65nm CMOS process and measurement results show a phase noise of −96dBc/Hz at 60GHz while consuming 77.5mW from a 1.2V supply. To to authors knowledge this phase noise is about 20dB better then recently reported QPLL and about 10dB compared to düTerential PLL operating at similar frequency.

A 60GHz 16Gb/s 16QAM low-power direct-conversion transceiver using capacitive cross-coupling neutralization in 65 nm CMOS

This paper presents a 16QAM direct-conversion transceiver in 65nm CMOS, which is capable of 60-GHz wireless standards. The capacitive cross-coupling neutralization contributes a high common-mode rejection and a high reverse isolation, and a fully-balanced mixer can improve the error vector magnitude due to the reduced local leakage. The maximum data rates with an antenna built in a package are 10Gb/s in QPSK mode and 16Gb/s in 16QAM mode and the transmitter and the receiver consume 181mW and 138 mW, respectively.

A digitally-calibrated 20-Gb/s 60-GHz direct-conversion transceiver in 65-nm CMOS

This paper presents a digitally-calibrated 60-GHz direct-conversion transceiver. To improve the error vector magnitude (EVM) performance over the wide bandwidth, a digital calibration technique is applied. The 60-GHz transceiver implemented by 65 nm CMOS achieves the maximum data rates of 20 Gb/s in 16QAM mode. The transmitter and receiver consume 351 mW and 238 mW from 1.2 V supply, respectively. As a 60-GHz transceiver, the best Tx-to-Rx EVM performance of -26.2 dB is achieved for 16QAM 7Gb/s data rate.

Design optimization of voltage controlled oscillators in consideration of parasitic capacitance

This paper presents a study of design optimization of voltage-controlled oscillators. The phase noise of LC-type oscillators is basically limited by quality factor of inductors. It is experimentally known that higher-Q inductors can be achieved at higher frequencies while oscillation frequency is limited by parasitic capacitances. In this paper, the minimum transistor size and degradation of quality factor caused by the switched-capacitor array are analytically estimated, and the maximum oscillation frequency of VCOs is also derived from the equivalent circuit considering parasitic capacitances. According to the analytical evaluation, the phase noise of VCO using 65-nm CMOS is 2 dBc/Hz better than that of 180-nm CMOS.

An ultra-compact LC-VCO using a stacked-spiral inductor

This paper proposes an ultra compact LC-VCO. Due to the speed-up of CMOS digital circuits, jitter of ring oscillators is becoming a critical problem. Even though an LC-VCO has a better phase noise, a layout size of on-chip inductor is a problem as a clock generator. Thus, the proposed LC-VCO consists of a very compact stacked-spiral inductor and active components placed are beneath the inductor. The VCO is implemented by a 65-nm CMOS process, and the chip area is only 594µm2. This VCO achieves a phase noise of -93dBc/Hz@1MHz, power consumption of 0.36mW, and FOMA of 210dBc/Hz.

60 GHz injection locked frequency quadrupler with quadrature outputs in 65 nm CMOS process

This paper presents a LC-based sub-harmonic injection-locked frequency quadrupler which multiplies a 15 GHz input to 60 GHz quadrature(I/Q) output signals. The proposed quadrupler can use a lower-frequency PLL for incident signal than doublers and triplers, which is very advantageous to implement a wide-tuning and low-phase-noise PLL. The proposed frequency quadrupler is implemented by using a 65nm CMOS process. It consumes 5.9mW with a 0.6V supply voltage, and the core layout area is 160 µm × 110 µm.