Shoichiro Kawashima

A charge-transfer amplifier and an encoded-bus architecture for low-power SRAM's

This paper proposes and reports a low-power SRAM using a charge-transfer (CT) pre-sense amplifier and a bus signal encoding scheme. The CT amplifier overcomes the V/sub th/ relative difference between the pair MOS transistors, and thus reduces the input offset voltage. The encoded-bus scheme reduces the number of signals being switched to cut the capacitive load. These read-path dynamic circuits have eight-timings which a low-power DLL produces. The fabricated 0.35-/spl mu/m-rule 2k-by-16-bit SRAM operated at 50 MHz with the power dissipation of 5 mW at 1 V.

A ferroelectric memory-based secure dynamically programmable gate array

A nonvolatile ferroelectric SRAM based 8-context dynamically programmable gate array enables low-cost field programmable systems by the elimination of off-chip nonvolatile memories. Read and program procedures of the associated configuration memory are securely protected, so that unauthorized users cannot gain access to configuration data. The ferroelectric SRAM configuration memory features 2ns nondestructive read operations along with stable data recall. The logic block circuit is optimized to improve available logic gates for multi-context scheme.

A current-based reference-generation scheme for 1T-1C ferroelectric random-access memories

A reference generation scheme is proposed for a 1T-1C ferroelectric random-access memory (FeRAM) architecture that balances fatigue evenly between memory cells and reference cells. This is achieved by including a reference cell per row (instead of per column) of the memory array. The proposed scheme converts the bitline voltage to current and compares this current against a reference current using a current-steering sense amplifier. This scheme is evaluated over a range of bitline lengths and cell sizes in a 16-Kb test chip implemented in a 0.35-/spl mu/m FeRAM process. The test chip measures an access time of 62 ns at room temperature using a 3-V power supply.

Ferroelectric memory based secure dynamically programmable gate array

A nonvolatile ferroelectric SRAM based 8-context dynamically programmable gate array enables low-cost field programmable systems by the elimination of off-chip nonvolatile memories. Read and program procedures of the associated configuration memory are securely protected, so that unauthorized users cannot gain access to configuration data. The ferroelectric SRAM configuration memory features 2ns nondestructive read operations along with stable data recall. The logic block circuit is optimized to improve available logic gates for multi-context scheme.

Development of ferroelectric RAM (FRAM) for mass production

We have developed ferroelectric capacitor fabrication technique and a new sensing amplifier circuit to realize low-voltage and high-density FRAM. Improvement of IrO, top electrode near the ferroelectric interface successively lowers operation voltage. And our developed “Dual Reference Sensing Amplifier” enables to commercialize highly-reliable FRAM with memory density of 4Mb or larger.

Circuit implementations of the differential capacitance read scheme (DCRS) for ferroelectric random-access memories (FeRAM)

This paper presents two circuit implementations for the differential capacitance read scheme (DCRS) in ferroelectric random-access memories (FeRAM). Compared to the conventional read scheme, DCRS achieves a faster read access by activating the sense amplifiers immediately after a wordline is activated. By relying on the capacitance difference instead of the charge difference, DCRS avoids raising the highly capacitive platelines until after the read is complete. We have implemented this scheme in a 0.35-/spl mu/m CMOS+Ferro test chip that includes an array of 256 /spl times/ 32 2T-2C cells. The test chip measures an access time of 45 ns at a power supply of 3 V.

A differential-capacitance read scheme for FeRAMs

A differential-capacitance read scheme keeps the plateline voltage constant at ground and begins sensing the stored data immediately after a wordline is raised, hence eliminating the time spent in conventional read schemes in raising the highly capacitive plateline and in charge sharing of the bitlines with the ferroelectric capacitors. The proposed read scheme is used in a 256/spl times/128-bit testchip that features both 2T-2C and 1T-1C cells in 0.35/spl mu/m technology. The read scheme achieves a 40% reduction in access time.

A Triple-Protection Structured COB FRAM with 1.2-V Operation and 1017-Cycle Endurance

We have developed a ferroelectric RAM (FRAM) with a low operation voltage of 1.2 V and a high switching endurance up to 1017 cycles. Our newly developed triple-protection structured cell array, has constructed without an additional mask step, effectively protects 0.4-μm2 ferroelectric capacitors from hydrogen and moisture degradation. We have designed our capacitor-over-bit-line (COB) structure to have a small cell size of 0.5 μm2.