Kazuaki Takai

Influence of Electrode Contacts on Leakage Current of SrTiO3 Capacitors

The current-voltage (I-V) characteristics of capacitors using SrTiO3 film were investigated. Rectification characteristics were observed, either when oxygen gas was introduced during sputter deposition of top electrodes, or when the SrTiO3 film was annealed in oxygen. These I-V characteristics are attributed to blocking contacts between SrTiO3 and the electrodes. It is considered that such contacts are formed because of the reduction of the crystal defects in SrTiO3 films, and they have decisive influence on the leakage current of the capacitor.

FRAM technologies compatible with 0.5-um CMOS logics

We developed FRAM (FRAM is a registered trademark of Ramtron International Corporation that stands for FeRAM) technologies that are fully compatible with half-micron CMOS logics. The technologies achieve 1T/1C FRAM cell 12.5 micrometer2 in a size and 68k-FRAM embedded 8bit-MCU. The CMOS transistors work at 5V for a cell operation and 3V for a logic operation. We did not use a COB to employ a present CMOS processing, and used the local interconnect to reduce a chip size. We used the W plug to contact to deep diffusion layers through high-aspect contact holes. The CMP planarization was used to relax PZT deposition and Pt etching. To prevent the process degradation of PZT, we used single Al wiring with SOG as an interlayer dielectric. The cover dielectric was formed with plasma TEOS- CVD without SiN to prevent the process degradation at this case. The SiN cover will be indispensable in real products. These technologies achieved a cell size 6.95 X 1.8 equals 12.5 (micrometer2) for 1T/1C and 4.2 X 6.5 equals 27.3(micrometer2) for 2T/2C that are the smallest cell size in FRAMs that do not use a COB structure and a poly-plug as a storage.

Control of La-doped Pb(Zr,Ti)O3 crystalline orientation and its influence on the properties of ferroelectric random access memory

We investigated the crystallization mechanisms of sputter-deposited La-doped Pb(Zr,Ti)O3 (PLZT) on a Pt/Ti metal stack in the postdeposition annealing (PDA) at 600 °C in O2-mixed Ar ambient. As-deposited amorphous PLZT generally transforms to a perovskite phase over 550 °C through a metastable pyrochlore phase during the PDA. We found that the O2 content of the PDA ambient crucially affects the pyrochlore-perovskite transformation (PPT) speed. While an O2 content much higher than 2% of the PDA ambient suppresses PPT, an O2 content much lower than 2% enhances PPT. An O2 content around of 2% of the PDA suppresses PPT near the surface of PLZT and simultaneously keeps PPT fast in the inner regions of PLZT in the pyrochlore phase because of the O2 diffusion limit from the PLZT surface, eventually resulting in almost only the growth of highly {111} oriented columnar PLZT on Pt, which reveals better electric properties than those obtained by the PDA with the ambient of O2 contents much higher or lower than 2%.

A Triple-Protection Structured COB FRAM with 1.2-V Operation and 1017-Cycle Endurance

We have developed a ferroelectric RAM (FRAM) with a low operation voltage of 1.2 V and a high switching endurance up to 1017 cycles. Our newly developed triple-protection structured cell array, has constructed without an additional mask step, effectively protects 0.4-μm2 ferroelectric capacitors from hydrogen and moisture degradation. We have designed our capacitor-over-bit-line (COB) structure to have a small cell size of 0.5 μm2.

MOVPE Growth of GaAs on Si Using Tertiarybutylarsine

We developed GaAs heteroepitaxy on a Si substrate by metalorganio vapor phase epitaxy (MOVPE) using tertiarybutylarsine (TBAs). When we preheated Si at 1000oC in the atmosphere including TBAs, a carbide layer was formed on the Si surface. This led to polycrystalline GaAs growth. By carrying out high-temperature preheating in an H 2 -only atmosphere and supplying TBAs after the preheating, we have successfully grown single-crystal GaAs with a mirror surface in a process completely free of AsH 3 .