Shoji Ushio

Surface Phase Diagram of 4H-SiC {0001} Step-Terrace Structures during Si-Vapor Etching in a TaC Crucible

Step-terrace structures were observed at on-axis/4o off 4H-SiC {0001} surfaces after Si-vapor etching which we have been supposed as an original technique to planarize and etch the SiC surfaces by utilizing a TaC crucible in temperature ranged from 1600 to 2200 oC. The structures obtained after the Si-vapor etching obviously indicated temperature dependence. There were two types of step-terrace structures in terms of the step height and the shape of the step edges at on-axis surfaces. Step bunched surfaces consisting of full unit cell height (= 1.0 nm) steps with {1-10n} facets at the step edges were observed at 4H-SiC (0001) in lower temperatures below 2000 oC, while smooth isotropic surfaces with half unit cell height (= 0.5 nm) steps and without any stable facets at the step edges were observed at 4H-SiC (0001) in higher temperatures above 2000 oC and in all temperature conditions (1600 - 2200 oC) at 4H-SiC (000-1). Similar tendency was also confirmed at 4o off 4H-SiC {0001} surfaces. From the comparison with 6H-SiC, macro step bunching (~10 nm height) was revealed to be a unique phenomenon at 4H-SiC (0001) surface in the etching.

Tunneling Atomic Force Microscopy Studies on Surface Growth Pits Due to Dislocations in 4H-SiC Epitaxial Layers

The morphological and electrical properties of surface growth pits caused by dislocations in 4H-SiC epitaxial layers were characterized using tunneling atomic force microscopy. The characteristic distribution of the tip current between the metal-coated atomic force microscopy tip and the SiC was observed within a large surface growth pit caused by a threading screw dislocation. The current was highly localized inside the pit and occurred only on the inclined surface in the up-step direction near the pit bottom. This paper discusses the causes and possible mechanisms of the observed tip current distribution inside surface growth pits.

4H-SiC(0001) Basal Plane Stability during the Growth of Epitaxial Graphene on Inverted-Mesa Structures

The epitaxial graphene growth at the 4H-SiC(0001) surface with intentionally inserted step-free basal plane regions was performed by high temperature annealing in the range of 1600–1900 °C under ultrahigh vacuum. For fabricating inverted-mesa structures with the step-free regions at SiC surfaces, a combined process consisting of a direct laser digging and a Si-vapor etching at 1900 °C was utilized. The graphitized surfaces were characterized by atomic force microscopy, low acceleration voltage (0.1–1.0 kV) scanning electron microscopy and Raman spectroscopy. It was found that the graphene thickness at the SiC step-free surface tends to be suppressed compared with the thickness at background SiC step-terrace surfaces where the steps are intrinsically introduced from intentional/unintentional substrate miscut angles. From the characterization by Raman mapping, 1 ML graphene was obtained at the SiC step-free surface at 1600 °C graphitization in contrast to the case that multilayer graphene was grown at SiC step-terrace surfaces.

A Highly Sensitive Inorganic Resist for Directly Fabricating Thermally Stable Oxide Pattern on Si Substrate by Low-Energy Electron-Beam Direct Writing

A simple process of 1-keV-range low-energy electron-beam direct writing (LE-EBDW) is proposed for a direct pattern of a thermally stable oxide layer on a Si substrate. An ultrathin multilayered structure is used as a highly sensitive inorganic negative resist for LE-EBDW, and it consists of an amorphous GaAs layer of 3 nm thick and its surface oxide. The EB-irradiated area is transformed into a thermally stable oxide pattern by heating the substrate to 750 °C in a vacuum after LE-EBDW. The heating process induces removal of the multilayered structure, while the oxide pattern can remain on the substrate. The remaining pattern can directly act as an ultrathin template for successive selective area growth on the Si substrate. It is assumed that the pattern is composed of thermally stable oxides such as SiO2 and Ga2O3 formed below the amorphous layer, not the surface oxide, of the multilayered structure.

Spatially Graded Graphitization on 4H-SiC (0001) with Si-Sublimation Gradient for High Quality Epitaxial Graphene Growth

We report a new approach to produce high quality epitaxial graphene based on the concept of controlling Si sublimation rate from SiC surface. By putting a mask substrate to suppress Si sublimation from the SiC surface in ultrahigh vacuum, epitaxial graphene growth at 4H-SiC (0001) was locally controlled. Spatially graded surface graphitization was confirmed in a scanning electron microscopy contrast from the outside unmasked region to the inside masked region. The contrast was discussed with Raman characterization as the increase of graphene thickness and the surface compositional change of SiC. Results indicate two types of growth processes of epitaxial graphene at 4H-SiC (0001) step-terrace structures.

The Formation of an Epitaxial-Graphene Cap Layer for Post-Implantation High Temperature Annealing of SiC and its In Situ Removal by Si-Vapor Etching

As a new graphene functionality applicable to post-implantation high temperature annealing of SiC, a method of in situ formation and removal of large area epitaxial few-layer graphene on 4H-SiC(0001) Si-face is proposed. It is demonstrated that the homogeneous graphene layer formed by Si sublimation can be preserved without the decomposition of the underlying SiC substrate even in the excess of 2000 oC in ultrahigh vacuum. It is due to the existence of the stable (6√3×6√3) buffer layer at the interface. To ensure this cap function, the homogeneity of the interface must be guaranteed. In order to do that, precise control of the initial SiC surface flatness is required. Si-vapor etching is a simple and versatile SiC surface pre/post- treatment method, where thermally decomposed SiC surface is compensated by a Si-vapor flux from Si solid source in the same semi-closed TaC container. While this Si-vapor etching allows precise control of SiC etch depth and surface step-terrace structures, it also provides a “decap” function to remove of the graphene layer. The surface properties after the each process were characterized by AFM and Raman spectroscopy.

Effect of Al Concentration in AlGaAs Oxide Mask Pattern on Faceting Kinetics during Selective Area Growth of GaAs by Molecular Beam Epitaxy

An oxidized AlGaAs layer is used as an inorganic negative resist for low-energy electron-beam lithography. The patterned oxide can function as an ultrathin template for selectively growing GaAs mesa structures having side facets vertical to a GaAs(001) substrate by molecular beam epitaxy. With increase in the Al concentration in the oxide, the geometric shape of the structures with lateral growth on the oxide surface changes from triangular to pentagonal. This change is explained by a minimization effect of the total surface energy of the structure, including the interfacial energy between the lateral growth region and the patterned oxide mask.