Shota Ishihara

A Low-Power FPGA Based on Autonomous Fine-Grain Power Gating

This paper presents a field-programmable gate array (FPGA) based on lookup table level fine-grain power gating with small overheads. The power gating technique implemented in the proposed architecture can directly detect the activity of each look-up-table easily by exploiting features of asynchronous architectures. Moreover, detecting the data arrival in advance prevents the delay increase for waking-up and the power consumption of unnecessary power switching. Since the power gating technique has small overheads, the granularity size of a power-gated domain is as fine as a single two-input and one-output lookup table. The proposed FPGA is fabricated using the ASPLA 90-nm CMOS process with dual threshold voltages. We use an image processing application called “template matching” for evaluation. Since the proposed FPGA is suitable for processing where the workload changes dynamically, an adaptive algorithm where a small computational kernel is employed. Compared to a synchronous FPGA and an asynchronous FPGA without power gating, the power consumption is reduced respectively by 38% and 15% at 85°C.

A low-power FPGA based on autonomous fine-grain power-gating

This is the first implementation of an FPGA based on autonomous fine-grain power-gating. To cut the power consumption of clock network and detect the activity of the cell efficiently, asynchronous architecture is full exploited. The proposed FPGA is fabricated in a 90nm CMOS process with dual threshold voltages. It is more efficient in power than the synchronous FPGA at less than 30% utilization.

Evaluation of a Field-Programmable VLSI Based on an Asynchronous Bit-Serial Architecture

This paper presents a novel asynchronous architecture of field-programmable gate arrays (FPGAs) to reduce the power consumption. In the dynamic power consumption of the conventional FPGAs, the power consumed by the switch blocks and clock distribution is dominant since FPGAs have complex switch blocks and the large number of registers for high programmability. To reduce the power consumption of switch blocks and clock distribution, asynchronous bit-serial architecture is proposed. To ensure the correct operation independent of data-path lengths, we use the level-encoded dual-rail encoding and propose its area-efficient implementation. The proposed field-programmable VLSI is implemented in a 90 nm CMOS technology. The delay and the power consumption of the proposed FPVLSI are respectively 61% and 58% of those of 4-phase dual-rail encoding which is the most common encoding in delay sensitive encoding.

A low-power field-programmable VLSI based on a fine-grained power-gating scheme

This paper presents a novel asynchronous architecture of field-programmable gate arrays (FPGAs) to reduce the power consumption. To reduce the power consumption of switch blocks and clock distribution, asynchronous bit-serial architecture is proposed. To reduce the static power due to leakage current that is now comparable to the dynamic one, we propose a fine-grained power-gating scheme at each Look-up table (LUT). The proposed field-programmable VLSI is fabricated in a 90 nm CMOS technology. Its power consumption is reduced to 42% compared to synchronous architecture.

A Field-programmable VLSI based on an asynchronous bit-serial architecture

SUMMARY This paper presents a novel asynchronous architecture of Field-programmable gate arrays (FPGAs) to reduce the power consumption. In the dynamic power consumption of the conventional FPGAs, the power consumed by the switch blocks and clock distribution is dominant since FPGAs have complex switch blocks and the large number of registers for high programmability. To reduce the power consumption of switch blocks and clock distribution, asynchronous bit-serial architecture is proposed. To ensure the correct operation independent of data-path lengths, we use the level-encoded dual-rail encoding and propose its area-efficient implementation. The proposed field-programmable VLSI is implemented in a 90 nm CMOS technology. The delay and the power consumption of the proposed FPVLSI are respectively 61% and 58% of those of 4-phase dual-rail encoding which is the most common encoding in delay insensitive encoding.

Evaluation of a Self-Adaptive Voltage Control Scheme for Low-Power FPGAs

This paper presents a fine-grain supply- voltage-control scheme for low-power FPGAs. The proposed supply-voltage-control scheme detects the critical path in real time with small overheads by exploiting features of asynchronous architectures. In an FPGA based on the proposed supply-voltage- control scheme, logic blocks on the sub-critical path are autonomously switched to a lower supply voltage to reduce the power consumption without system performance degradation. Moreover, in order to reduce the overheads of level shifters used at the power domain interface, a look-up-table without level shifters is employed. Because of the small overheads of the proposed supply-voltage-control scheme and the power domain interface, the granularity size of the power domain in the proposed FPGA is as fine as a single four-input logic block. The proposed FPGA is fabricated using the e-Shuttle 65 nm CMOS process. Correct operation of the proposed FPGA on the test chip is confirmed.

Dual-rail/single-rail hybrid logic design for high-performance asynchronous circuit

This paper presents a fine-grain pipelined asynchronous circuit that uses a mixture of dual-rail and single-rail logic. Dual-rail logic is limited to construct a stable critical path. Based on this critical path, the handshake control circuit is greatly simplified, which improves the performance of speed and power consumption. On the other hand, non-critical paths are composed of single-rail logic which has small logic overhead and the entire pipelined circuit has no intermediate registers or latches. To evaluate the proposed design method, an array style multiplier is designed and simulated in a 65nm design rule. The multiplier works as high as 4.35G data-set/s. Compared to the classical synchronous circuit, the proposed circuit has no active power consumption when there are no data operation. Even the circuits work at peak speed, the proposed circuit still reduces the power consumption by 35%.

Architecture of a low-power FPGA based on self-adaptive voltage control

This paper presents a low-power FPGA with multiple supply voltages. In the proposed FPGA, the supply voltage of each logic block is self-adaptive to the workload, data path and temperature to minimize the power consumption without system performance degradation. In the self-adaptive voltage control scheme, features of the asynchronous architecture are exploited. The data arrival of the asynchronous architecture can be easily detected by detecting the change of the datas phase. By exploiting this feature, the critical path can be detected in real time. Logic blocks on the non-critical path are autonomously switched to a lower supply voltage to reduce the power consumption.

An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture

This paper presents an asynchronous FPGA that combines four-phase dual-rail encoding and LEDR (Level-Encoded Dual-Rail) encoding. Four-phase dual-rail encoding is used for small area and low power of function units, while LEDR encoding for high throughput and low power of data transfer. The proposed FPGA is fabricated in the e-Shuttle 65nm CMOS process and operates at 870 MHz. Compared to the synchronous FPGA, the power consumption is reduced by 38% for the workload of 15%.