Michitaka Kameyama

A 200 MHz pipelined multiplier using 1.5 V-supply multiple-valued MOS current-mode circuits with dual-rail source-coupled logic

A new multiple-valued current-mode MOS integrated circuit is proposed for high-speed arithmetic systems at low supply voltage. Since a multiple-valued source-coupled logic circuit with dual-rail complementary inputs results in a small signal-voltage swing while providing a constant driving current, the switching speed of the circuit is improved at low supply voltage. As an application to arithmetic systems, a 200 MHz 54/spl times/51-b pipelined multiplier using the proposed circuits with a 1.5 V supply voltage is designed with a 0.8-/spl mu/m standard CMOS technology. The performance of the proposed multiplier is evaluated to be about 1.4 times faster than that of a corresponding binary implementation under the normalized power dissipation. A prototype chip is also fabricated to confirm the basic operation of the multiple-valued arithmetic circuit.

VLSI processor for reliable stereo matching based on adaptive window-size selection

Stereo vision is a well known method to acquire 3D information. One important problem in stereo vision is to establish reliable correspondence between images. Another problem is that the correspondence search is time-consuming. This paper presents a reliable stereo-matching algorithm and a new parallel VLSI processor architecture for stereo matching. One commonly-used method to establish correspondence between images is the SAD (sum of absolute differences) method. A window size is iteratively enlarged to select as small a window for each pixel as possible that can avoid ambiguity based on uniqueness of a minimum of an SAD graph. This process is called a global search. Next, the estimate of the corresponding pixel obtained by the global search is iteratively refined by shrinking the window size. To avoid ambiguity with a small window size, the correspondence estimate obtained by the global search is efficiently used. The proposed algorithm has regular data flow based on iterations of SAD computation so that it is suitable for parallel processing.

Fully source-coupled logic based multiple-valued VLSI

A novel source-coupled logic (SCL) style using multiple-valued signals, called multiple-valued source-coupled logic (MVSCL), which operates with an input voltage swing of about 0.3 V is proposed for high-speed and low-power VLSI systems. A multiple-valued comparator which is a key component, is realized by using differential-pair circuits (DPCs), so that its power dissipation can be greatly reduced while maintaining high-speed switching. Moreover, the current-source control allows steady current flow to cut off when the circuit is not active, thereby saving power dissipation. A 54/spl times/54-bit signed-digit multiplier based on MVSCL is designed in a 0.35 /spl mu/m CMOS technology, and its performance is superior to both corresponding binary static CMOS and multiple-valued current-mode (MVCM) implementation.

Design of a one-transistor-cell multiple-valued CAM

A new high-density multiple-valued content-addressable memory (CAM) is proposed to perform highly parallel search operations in a limited chip area. The number of cells in the CAM is reduced by the use of multiple-valued data representation. Moreover, multiple-valued stored data correspond to the threshold voltage of a floating-gate MOS transistor, so that the cell circuit can be designed using only a single transistor. As a result, the cell area of the proposed four-valued CAM is reduced to 14% of that of a conventional dynamic binary CAM, and its performance is about 5.4-times higher than that of the corresponding binary one under a 0.8-/spl mu/m standard EEPROM technology.

Multiple-valued dynamic source-coupled logic

A new multiple-valued current-mode (MVCM) integrated circuit based on dynamic source-coupled logic (SCL) is proposed for low-power VLSI applications. The use of a precharge-evaluate logic style makes steady current flow cut off, thereby greatly saving the power dissipation. A combination of SCL and dynamic logic styles makes it possible to reduce the power dissipation while maintaining a highspeed switching capability due to small input-voltage swing with SCL. As a typical example of a high-performance arithmetic circuit, a radix-2 signed-digit adder based on the proposed dynamic SCL is implemented in a 0.18-/spl mu/m CMOS technology. Its power dissipation is reduced to about 33 percent in comparison with that of the corresponding binary CMOS implementation under the normalized switching delay.

Multiple-valued logic-in-memory VLSI based on a floating-gate-MOS pass-transistor network

A logic-in-memory structure, in which storage functions are distributed over a logic-circuit plane, is a solution to the communication bottleneck between memory and logic modules, one of the most serious problems in recent deep submicron VLSI systems technology. This logic-in-memory VLSI based on floating-gate MOS transistors merges storage and switching functions in a multiple-valued-input and binary-output combinational logic circuit that is useful for the realization of parallel arithmetic and logic circuits. The paper presents a general structure of a 4-valued-input and binary-output combinational logic circuit. It has two kinds of inputs, external and stored constant inputs. In the logic-in-memory VLSI, a large number of stored data are distributed in not only word-parallel but also in digit parallel manners.

Reliable stereo matching for highly-safe intelligent vehicles and its VLSI implementation

To realize highly-safe intelligent vehicles, high-speed acquisition of reliable 3D information is essential. A major issue of stereo vision is to establish reliable correspondence between images. This paper presents a reliable stereo-matching algorithm based on SAD (sum of absolute differences) computation. Reliable correspondence can be established by selecting a desirable window size of the SAD computation based on the uniqueness of a minimum of the SAD graph. A pixel-serial and window-parallel architecture is also proposed to achieve 100% utilization of processing elements. The performance of the VLSI processor is evaluated to be more than ten thousand times higher than that of a general-purpose processor.

High-performance field programmable VLSI processor based on a direct allocation of a control/data flow graph

This paper proposes a high-performance field programmable VLSI processor (FPVLSI), in which a bit-serial processing element (PE) array is introduced to reduce the complexity of programmable interconnection networks. Therefore, the area and delay of a switch block in the interconnection network can be greatly reduced. Moreover, direct allocation of a control/data flow graph is employed where only a single node is mapped into a PE so that the wiring complexity is greatly reduced. The FPVLSI with 4400 PEs is designed in a 0.35 /spl mu/m CMOS process. The performance of the FPVLSI is evaluated to be 28 times higher than that of the typical FPGA when executing the 16-point FFT.

Ferroelectric-based functional pass-gate for fine-grain pipelined VLSI computation

The state-transition scheme of remnant polarization in a ferroelectric capacitor performs storage and switching functions simultaneously with a functional pass-gate. As an example of fine-grain pipelined VLSI computation, a 250 MHz 54/spl times/54 b pipelined multiplier has 2.5 W estimated power dissipation in a 0.6 /spl mu/m ferroelectric/CMOS technology.

Design of multiple-valued linear digital circuits for highly parallel k-ary operations

To design highly parallel digital circuits such as an adder and a multiplier, it is difficult to find the optimal code assignment in the nonlinear digital system. On the other hand, the use of the linear concept in digital systems seems to be very attractive because analytical methods can be utilized. For unary operations, the design method of locally computable circuits have been discussed. In this paper, we propose a new design method of highly parallel multiple-valued linear digital circuits for k-ary operations using the concept of identification of input-output graphs by the introduction of multiplicated redundant symbols.<<ETX>>