Shotaro Takeuchi

Growth of highly strain-relaxed Ge1−xSnx/virtual Ge by a Sn precipitation controlled compositionally step-graded method

We have investigated Sn precipitation and strain relaxation behaviors in the growth of Ge1−xSnx layers on virtual Ge substrates (v-Ge) for strain engineering of Ge. By varying misfit strain at Ge1−xSnx∕v-Ge and Ge1−ySny∕Ge1−xSnx interfaces, we found that a critical misfit strain controls the onset of Sn precipitation at a given thickness of the Ge1−xSnx layer. A compositionally step-graded method, in which the critical misfit strain is taken into account, was applied to the growth of strain-relaxed Ge1−xSnx layers on v-Ge. Postdeposition annealing at each growth step led to lateral propagation of threading dislocations preexisting in the layer and originating from v-Ge, which resulted in high degree of strain relaxation. An epitaxial Ge layer was grown on the strain-relaxed Ge1−xSnx layer and an in-plane tensile strain of 0.68% was achieved.

High Quality Ge Virtual Substrates on Si Wafers with Standard STI Patterning

Further improving complementary metal oxide semiconductor performance beyond the 22 nm generation likely requires the use ofhigh mobility channel materials, such as Ge for p-type metal oxide semiconductor pMOS and III/V for n-type metal oxidesemiconductor devices. The complementary integration of both materials on Si substrates can be realized with selective epitaxialgrowth. We present two fabrication schemes for Ge virtual substrates using Si wafers with standard shallow trench isolation STI .This reduces the fabrication cost of these virtual substrates as the complicated isolation scheme in blanket Ge can be omitted. Thelow topography enables integration of ultrathin high-

Growth and structure evaluation of strain-relaxed Ge1−xSnx buffer layers grown on various types of substrates

We have performed growth and structure evaluation of strain-relaxed Ge1−xSnx buffer layers grown on Si(0 0 1), virtual Ge(0 0 1) and bulk Ge(0 0 1) substrates. In the case of Si(0 0 1), amorphous Ge1−xSnx phases are partially formed as well as many threading dislocations in Ge0.98Sn0.02 layers. Employing virtual Ge substrates to reduce the lattice mismatch at the interface leads to epitaxial Ge0.978Sn0.022 layers with a flat surface. Most of threading dislocations in the Ge0.978Sn0.022 layer comes from pre-existing ones in the virtual Ge substrate and propagates laterally, leaving misfit segments at the Ge0.978Sn0.022/virtual Ge interface, after post-deposition annealing (PDA). This simultaneously results in the reduction of threading dislocation density and the promotion of strain relaxation. In the case of bulk Ge(0 0 1), although low threading dislocation density can be achieved, less than 106 cm−2, the film exhibits surface undulation and a lesser degree of strain relaxation even after PDA.

Mobility Behavior of Ge1-xSnx Layers Grown on Silicon-on-Insulator Substrates

We have investigated the behaviors of the carrier mobility and concentration of the undoped Ge1-xSnx layers epitaxially grown on silicon-on-insulator (SOI) substrates. Hall measurement revealed the conduction of holes excited from acceptor levels related to vacancy defects whose concentration was as high as 1018 cm-3 in Ge1-xSnx layers. The temperature dependences of the carrier mobility and concentration in the valence band was estimated by reducing the parallel conduction component in the impurity band. The incorporation of Sn at a content lower than 4.0% hardly degraded the hole mobility of heteroepitaxial Ge1-xSnx layers. In contrast, the mobility of the Ge1-xSnx layers was improved by reducing the carrier concentration of the Ge1-xSnx layers by Sn incorporation compared with that of the Ge layer formed under the same growth and annealing conditions. This result suggests that the incorporation of Sn into Ge leads to reducing the hole concentration of the electrically active vacancy defects due to the formation of Sn-vacancy pairs.

Molecular beam deposition of Al2O3 on p-Ge(001)/Ge0.95Sn0.05 heterostructure and impact of a Ge-cap interfacial layer

We investigated the molecular beam deposition of Al2O3 on Ge0.95Sn0.05 surface with and without an ultra thin Ge cap layer in between. We first studied the atomic configuration of both Ge1−xSnx and Ge/Ge1−xSnx surfaces after deoxidation by reflection high-energy electron diffraction and resulted, respectively, in a c(4×2) and (2×1) surface reconstructions. After in situ deposition of an Al2O3 high-κ gate dielectric we evidenced using time-of-flight secondary ion mass spectroscopy analyses that Sn diffusion was at the origin of high leakage current densities in the Ge1−xSnx/Al2O3 gate stack. This damage could be avoided by inserting a thin 5-nm-thick Ge cap between the oxide and the Ge1−xSnx layer. Finally, metal-oxide-semiconductor capacitors on the Ge capped sample showed well-behaved capacitance-voltage (C-V) characteristics with interface trap density (Dit) in the range of 1012 eV−1 cm−2 in mid gap and higher close to the valence band edge.

Phonon transport control by nanoarchitecture including epitaxial Ge nanodots for Si-based thermoelectric materials.

Phonon transport in Si films was controlled using epitaxially-grown ultrasmall Ge nanodots (NDs) with ultrahigh density for the purpose of developing Si-based thermoelectric materials. The Si/Ge ND stacked structures, which were formed by the ultrathin SiO2 film technique, exhibited lower thermal conductivities than those of the conventional nanostructured SiGe bulk alloys, despite the stacked structures having a smaller Ge fraction. This came from the large thermal resistance caused by phonon scattering at the Si/Ge ND interfaces. The phonon scattering can be controlled by the Ge ND structure, which was independent of Si layer structure for carrier transport. These results demonstrate the effectiveness of ultrasmall epitaxial Ge NDs as phonon scattering sources, opening up a route for the realisation of Si-based thermoelectric materials.

Vapor phase doping with N-type dopant into silicon by atmospheric pressure chemical vapor deposition

Atomic layer doping of phosphorus (P) and arsenic (As) into Si was performed using the vapor phase doping (VPD) technique. For increasing deposition time and precursor gas flow rate, the P and As doses tend to saturate at about 0.8 and 1.0 monolayer of Si, respectively. Therefore, these processes are self-limited in both cases. When a Si cap layer is grown on the P-covered Si(001), high P concentration of 3.7 × 10 20 cm -3 at the heterointerface in the Sicap/P/Si-substrate layer stacks is achieved. Due to As desorption and segregation toward the Si surface during the temperature ramp up and during the Si-cap growth, the As concentration at the heterointerface in the Si-cap/As/Si-substrate layer stacks was lower compared to the P case. These results allowed us to evaluate the feasibility of the VPD process to fabricate precisely controlled doping profiles.

Si/SiGe Resonant Interband Tunneling Diodes Incorporating

This is the first report of a Si/SiGe resonant interband tunneling diodes (RITDs) on silicon substrates grown by the chemical vapor deposition process. The nominal RITD structure forms two quantum wells created by sharp delta-doping planes which provide for a resonant tunneling condition through the intrinsic spacer. The vapor phase doping technique was used to achieve abrupt degenerate doping profiles at higher substrate temperatures than previous reports using low-temperature molecular beam epitaxy, and postgrowth annealing experiments are suggestive that fewer point defects are incorporated, as a result. The as-grown RITD samples without postgrowth thermal annealing show negative differential resistance with a recorded peak-to-valley current ratio up to 1.85 with a corresponding peak current density of 0.1 kA/cm2 at room temperature.

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The high electrical and drastically-low thermal conductivities, a vital goal for high performance thermoelectric (TE) materials, are achieved in Si-based nanoarchitecture composed of Si channel layers and epitaxial Ge nanodots (NDs) with ultrahigh areal density (~1012 cm−2). In this nanoarchitecture, the ultrasmall NDs and Si channel layers play roles of phonon scattering sources and electrical conduction channels, respectively. Electron conductivity in n-type nanoacrhitecture shows high values comparable to those of epitaxial Si films despite the existence of epitaxial NDs. This is because Ge NDs mainly scattered not electrons but phonons selectively, which could be attributed to the small conduction band offset at the epitaxially-grown Si/Ge interface and high transmission probability through stacking faults. These results demonstrate an independent control of thermal and electrical conduction for phonon-glass electron-crystal TE materials by nanostructure designing and the energetic and structural interface control.

-Doping Layers Grown by Chemical Vapor Deposition

A Si-based nanomaterial is proposed for use as a thermoelectric material. Ultrasmall epitaxial Ge nanodots (NDs) with an ultrahigh density are introduced into Si films as phonon scatterers using an ultrathin SiO2 film technique. The nanomaterial has the stacked structure Si/Ge NDs/Si on Si substrates. Reflection high-energy electron diffraction reveals epitaxial growth of the Ge NDs and Si layers in all of the stacking stages. Sharp interfaces of the Ge NDs/Si in the stacked structures were observed by high-angle annular field scanning transmission electron microscopy. The Ge NDs were controlled in terms of their composition and strain: main parts of the NDs did not alloy with Si, and the elastic strain was relaxed. These features were confirmed by Raman scattering and x-ray diffraction measurements. The fabrication techniques used to make the simple Si-based stacked structure with strain-relaxed almost pure Ge NDs are useful to develop thermoelectric nanomaterials.