Shouli Yan

A continuous-time sigma-delta modulator with 88-dB dynamic range and 1.1-MHz signal bandwidth

This paper presents the design and experimental results of a continuous-time /spl Sigma//spl Delta/ modulator for ADSL applications. Multibit nonreturn-to-zero (NRZ) DAC pulse shaping is used to reduce clock jitter sensitivity. The nonzero excess loop delay problem in conventional continuous-time /spl Sigma//spl Delta/ modulators is solved by our proposed architecture. A prototype third-order continuous-time /spl Sigma//spl Delta/ modulator with 5-bit internal quantization was realized in a 0.5-/spl mu/m double-poly triple-metal CMOS technology, with a chip area of 2.4 /spl times/ 2.4 mm/sup 2/. Experimental results show that the modulator achieves 88-dB dynamic range, 84-dB SNR, and 83-dB SNDR over a 1.1-MHz signal bandwidth with an oversampling ratio of 16, while dissipating 62 mW from a 3.3-V supply.

An RC time constant auto-tuning structure for high linearity continuous-time /spl Sigma//spl Delta/ modulators and active filters

An automatic RC time constant tuning scheme is proposed for high linearity continuous-time g/sub m/-C and active RC circuits in a low power consumption environment. Instead of changing the g/sub m/ (in g/sub m/-C filters), the RC time constant is tuned by discretely varying the integration capacitors to preserve a high linearity. The auto-tuning circuit, consisting of an analog integrator, a voltage comparator, and a digital tuning engine, generates a control word and sets on-chip capacitors to obtain an RC time-constant accuracy of /spl plusmn/2-10%. The proposed scheme is verified by the experimental results of a test chip in a 0.5 /spl mu/m CMOS technology. It achieves a peak S/(N+D) of 83 dB while a tuning range of over /spl plusmn/40% is accomplished.

Feedforward reversed nested Miller compensation techniques for three-stage amplifiers

Two novel reversed nested Miller compensation (RNMC) techniques for low-voltage three-stage amplifiers are proposed in this contribution: Nested Feedforward RNMC (NFRNMC) and Crossed Feedforward RNMC (CFRNMC). Both techniques employ double feedforward paths to remove the right-half-plane zero. The second architecture generates a left-half-plane zero to further improve the phase margin. To demonstrate advantages of the new RNMC techniques over the traditional RNMC architecture, two three-stage amplifiers are designed employing the proposed techniques in a standard 0.5 /spl mu/m CMOS process. Simulation results show that, with the same gain-bandwidth product, the NFRNMC and CFRNMC amplifiers have improved stabilities over the conventional RNMC amplifiers by more than 150 and 200 in the phase margin, respectively. They both dissipate less than 0.4 mW of power with a 1 V supply.

A continuous-time /spl Sigma//spl Delta/ modulator with 88dB dynamic range and 1.1MHz signal bandwidth

A baseband continuous-time multi-bit /spl Sigma//spl Delta/ modulator achieves 88dB dynamic range over a 1.1MHz signal bandwidth consuming 62mW from a 3.3V supply. Excess loop delay encountered in conventional continuous-time modulators is eliminated by the proposed architecture. Clock-jitter sensitivity is considerably reduced compared with prior designs.

A constant-g/sub m/ rail-to-rail op amp input stage using dynamic current scaling technique

We introduce an innovative constant-transconductance (g/sub m/) CMOS input stage. Rather than handling the tail currents of the input differential pairs, the proposed circuit scales the output signal currents of the input differential pairs dynamically for a constant g/sub m/ while keeping the tail currents of the input transistors unchanged. The operation of the new circuit does not rely on the quadratic characteristic of the input MOS devices, and is independent of the operating regions of the input transistors. The new constant-g/sub m/ scheme, which has potential for high-frequency applications, can be employed universally to both short and long channel transistors, and is suitable for new generations of deep submicrometer CMOS technologies. The technique is demonstrated through the design of a rail-to-rail CMOS op amp with supply voltage of 3 V in 0.35 /spl mu/m CMOS technology. Simulations show that, when the input common-mode voltage swings from rail to rail, the op amps input stage g/sub m/ varies around /spl plusmn/1.5% and /spl plusmn/2.9%, respectively, for input transistors in the strong and weak inversion regions.

A Robust and Scalable Constant-

In this paper, we propose a robust and scalable constant- rail-to-rail CMOS input stage for VLSI cell libraries. The proposed circuit does not rely on the characteristics and particular operation (strong, moderate, and weak inversion) regions of the input transistors and is insensitive to mismatches between p- and n-channel devices. Only standard CMOS transistors are used in the circuit without any special devices, such as floating-gate or depletion-mode transistors. Very small variations (less than ) have been achieved without sacrificing the large-signal behavior. The proposed circuit is proven effective for both long-channel and deep sub-micron CMOS technologies and is suitable for VLSI cell libraries, audio/video, embedded mixed-signal system-on-chip (SoC), and other applications. A prototype amplifier with rail-to-rail input common-mode range has been designed and fabricated in a standard 0.35-m CMOS technology. Experimental results confirm the effectiveness and robustness of proposed techniques.

g_m

A constant-gm input stage featuring both constant small signal and large signal behaviors over the entire input common-mode range is proposed in this brief. A novel static feedback loop is employed to minimize the N and P transconductance mismatch due to process and temperature variations. The output currents of the N and P differential pairs are dynamically steered to keep a constant gm and a constant slew rate. The overall technique is independent of the operation regions of input transistors, and does not rely on the quadratic characteristics of input MOS transistors. A prototype chip was designed for a 0.35-mum CMOS technology with 3-V power supply. The experimental results demonstrate that a constant-gm (plusmn3% variations) and a constant slew rate over the entire input common-mode range have been achieved

Rail-to-Rail CMOS Input Stage With Dynamic Feedback for VLSI Cell Libraries

We proposed a novel technique for low voltage rail-to-rail constant-g/sub m/ input stages, which does not depend on the operation regions of the MOS transistors. An op amp was designed to demonstrate the new idea using MOSIS AMJ 1.2 /spl mu/m technology. A 2.5 MHz unity-gain bandwidth with 61/spl deg/ phase margin was achieved when driving 10 k/spl Omega/ and 10 pF load, with 240 /spl mu/A current consumption and a power supply of 3 V. The g/sub m/ variation of the input stage is within /spl plusmn/3% from rail-to-rail. By changing the bias current, the unity-gain bandwidth could be programmed from 90 kHz to 3 MHz.

A Constant-

This paper presents a comparative study of a number of constant-transconductance (g/sub m/) techniques for CMOS amplifier input stages. The pros and cons of each technique are discussed. Theoretical analysis along with simulation results are discussed to demonstrate the performance of each constant-g/sub m/ technique. Finally, we propose a novel technique which achieves within /spl plusmn/3% g/sub m/ variation over the full input common-mode voltage range. The new technique exhibits improvement over other existing techniques.

g_{m}

In this paper, a discrete auto-tuning structure is proposed for continuous time sigma-delta AD converter (ADC) and applications that require high linearity, moderate precision in RC or C/g/sub m/ time constant. Comparison with continuous gm tuning and some other passive tuning implementations is also presented. A circuit is designed in 0.5 /spl mu/m CMOS process to examine the performance of the proposed circuit structure.