Bo Xia

A 3-V, 0.35-/spl mu/m CMOS Bluetooth receiver IC

This paper presents a monolithic low-IF Bluetooth receiver. The highlights of the receiver include a low-power active complex filter with a non-conventional tuning scheme and a high performance mixed-mode GFSK demodulator. The chip was fabricated on a 6.25 mm/sup 2/ die using TSMC 0.35 /spl mu/m standard CMOS process. -82 dBm sensitivity at 1e-3 BER, -10 dBm IIP3 and 15 dB noise figure were achieved In the measurements.

An RC time constant auto-tuning structure for high linearity continuous-time /spl Sigma//spl Delta/ modulators and active filters

An automatic RC time constant tuning scheme is proposed for high linearity continuous-time g/sub m/-C and active RC circuits in a low power consumption environment. Instead of changing the g/sub m/ (in g/sub m/-C filters), the RC time constant is tuned by discretely varying the integration capacitors to preserve a high linearity. The auto-tuning circuit, consisting of an analog integrator, a voltage comparator, and a digital tuning engine, generates a control word and sets on-chip capacitors to obtain an RC time-constant accuracy of /spl plusmn/2-10%. The proposed scheme is verified by the experimental results of a test chip in a 0.5 /spl mu/m CMOS technology. It achieves a peak S/(N+D) of 83 dB while a tuning range of over /spl plusmn/40% is accomplished.

A GFSK demodulator for low-IF Bluetooth receiver

An efficient mixed-mode Gaussian frequency-shift keying (GFSK) demodulator with a frequency offset cancellation circuit is presented. The structure is suitable for a low-IF Bluetooth receiver and can also be applied to other receivers involving continuous phase shift keying (CPSK) signals. The demodulator implementation is robust to tolerate process variations without requiring calibration. It can also track and cancel the time-varying local oscillator frequency offset between transmitter and receiver during the entire reception period. The chip was fabricated in CMOS 0.35-/spl mu/m digital process; it consumes 3 mA from a 3-V power supply and occupies 0.7 mm/sup 2/ of silicon area. A 16.2-dB input signal-to-noise ratio is obtained to achieve 0.1% bit-error rate as specified in Bluetooth specs. The co-channel interference rejection ratio is about 11 dB. Theoretical and experimental results are in good agreement.

A 10-bit 44-MS/s 20-mW configurable time-interleaved pipeline ADC for a dual-mode 802.11b/Bluetooth receiver

This work presents a configurable time-interleaved pipeline architecture as an efficient solution for the ADC design in high data rate multi-standard radios. The ADC is implemented in a 0.25-/spl mu/m BiCMOS process as part of an integrated dual mode 802.11b/Bluetooth direct conversion receiver. Its structure can be configured to accommodate the different sampling rate and dynamic range requirements of both standards. The different techniques employed at the system and circuit levels to optimize the power consumption are described. An on-line digital calibration scheme is also incorporated to assure the conversion linearity and reduce mismatch among the parallel branches. The proposed ADC is a switched-capacitor implementation occupying an area of 2.1 mm/sup 2/. It achieves 60 dB/64 dB dynamic range at 44 MHz/11 MHz sampling frequency with a power consumption of 20.2 mW/14.8 mW for the 802.11b/Bluetooth baseband signals.

Chameleon: a dual-mode 802.11b/Bluetooth receiver system design

In this paper, an approach to map the Bluetooth and 802.11b standards specifications into an architecture and specifications for the building blocks of a dual-mode direct conversion receiver is proposed. The design procedure focuses on optimizing the performance in each operating mode while attaining an efficient dual-standard solution. The impact of the expected receiver nonidealities and the characteristics of each building block are evaluated through bit-error-rate simulations. The proposed receiver design is verified through a fully integrated implementation from low-noise amplifier to analog-to-digital converter using IBM 0.25-/spl mu/m BiCMOS technology. Experimental results from the integrated prototype meet the specifications from both standards and are in good agreement with the target sensitivity.

A configurable time-interleaved pipeline ADC for multi-standard wireless receivers

A time-interleaved pipeline ADC is designed for an 802.11b/Bluetooth dual-mode receiver. Its operation mode can be configured to satisfy the resolution and sampling rate required by each standard. System and circuit level techniques are applied to optimize the ADC power dissipation. An on-line digital calibration scheme is developed to cancel both non-linearity and mismatch in the ADC. The measured dynamic range of the ADC is 60 dB at 44 MS/s and 64 dB at 11 MS/s over the 802.11b and Bluetooth signal bandwidth, respectively. The ADC consumes 14.8 mW in the Bluetooth mode and 20.2 mW in the 802.11b mode.

A monolithic CMOS low-IF Bluetooth receiver

A fully integrated low-IF CMOS Bluetooth receiver is presented. The IC is fabricated in TSMC 0.35 /spl mu/m standard CMOS process. The receiver consists of a radio frequency (RF) front end, a phase lock loop (PLL), an active complex filter, a GFSK demodulator and a frequency offset cancellation circuit. The experimental results show a -82 dBm sensitivity at le-3 BER, -10 dBm IIP3 and 15 dB noise figure.

A mixed-mode IF GFSK demodulator for Bluetooth

The paper describes a novel mixed-mode GFSK demodulator with a frequency offset cancellation circuit as part of a low-IF Bluetooth receiver. The demodulator is fabricated in TSMC 0.35 /spl mu/m standard CMOS process, consumes 3 mA from a 3 V power supply and occupies 0.7mm/sup 2/ of silicon area. For 10/sup -3/ BER as specified in Bluetooth standard, only 16.2 dB input SNR is required. The co-channel interference rejection is about 11 dB. The demodulator is robust to process technology variation, and no calibration is required. It can track and cancel the time-varying local oscillator (LO) frequency offset between transmitter and receiver during the whole reception time.

An auto-tuning structure for continuous time sigma-delta AD converter and high precision filters

In this paper, a discrete auto-tuning structure is proposed for continuous time sigma-delta AD converter (ADC) and applications that require high linearity, moderate precision in RC or C/g/sub m/ time constant. Comparison with continuous gm tuning and some other passive tuning implementations is also presented. A circuit is designed in 0.5 /spl mu/m CMOS process to examine the performance of the proposed circuit structure.

VLSI implementation of a neural network for solving linear second order parabolic PDE

Proposes an implementation of a cellular neural network to solve linear second order parabolic partial differential equations. This paper describes the underlying theory, circuit architecture and techniques employed to improve accuracy and throughput. A modified time-multiplexing scheme is applied to provide an area efficient solution. Simulation results and comparison are also included to illustrate the circuit performance.