Shoumian Chen

Optimization of BSIM3 I-V Model for Double Diffused Drain HV MOSFET

This paper presents a technique for modeling double diffused drain high-voltage MOSFET devices (DDD HV MOSFET). I-V measurements have been made by Agilent ICCAP. Based on the difference between DDD HV MOSFET and normal low voltage MOSFET devices (LV MOSFET), the Rd dependency of Vgs is discussed and equations of Rd and delta (the effective Vds parameter) in the BSIM3v3 model have been optimized. Three parameters are added: Prwg2 which is gate bias quadric coefficient of Rdsw and delta1, delta2 which are gate bias coefficients of delta. The optimization has been made on SPICE BSIM3v3 model using SPICE macro model. The contrast between I-V simulated data of optimized HV MOSFET model and the measured data has been made after parameters extraction. They fit very well

A Novel Structure On-Chip Spiral Inductors with Gradually Changed Metal Line Width and Space

A novel inductor layout structure with gradually reduced metal line width and space from outside to inside, which will ameliorate the metal loss issue of RF spiral inductor, is presented. The optimized inductors have shown less eddy-current effect than the conventional designs whose metal line width and space are normally fixed. Based on these kinds of advanced inductors, series resistance Rs could be reduced and at the same time, the quality factor of the inductor (Q) would be increased. The obtained results have corroborated the validity of the proposed method in the experiment, Q factor of a 5.96-nH new designed inductor on high-resistance silicon at 2.40 GHz is 14.23, 1.6% higher than the conventional structure with the same layout size. These novel inductors can be integrated with radio frequency integrated circuit (RF ICs) to gain better performance in RF front end of a wireless communication system

Analytical parameter extraction for NBTI reaction diffusion and trapping/detrapping models

Abstract Accurate parameters of negative bias temperature instability (NBTI) model are essential to predict the circuit lifetime during circuit design. This paper presents the extraction methods of NBTI model parameters for the NBTI reaction-diffusion (R-D) and trapping/detrapping (T/D) models. The R-D model parameters extraction mainly includes two steps: linear approximation and optimized extraction. In the first step, the term of ΔVth1/2n is described as approximately linear with t0.5 after the coordinate system conversion, where ΔVth is the degradation in threshold voltage and t is elapsing time. Then, the model parameters can be roughly calculated. In the second, an objective function of the genetic algorithm (GA) has been built up and its constraints can be determined by referring the values gotten from the first step. After solving the function, a set of accurate parameters of the NBTI model can be achieved. Similarly, the T/D model parameters extraction involves the curves fitting and further optimization based on the GA. Both the R-D and T-D extraction methods have been validated using a 40-nm CMOS process, and it is easy to implement the extraction procedures in a program extractor.

Extraction of geometry-related interconnect variation based on parasitic capacitance data

A new interconnect parasitic extraction flow considering geometry-related variation has been proposed in this letter. The 42 interconnect capacitance loads were fabricated by 55-nm process technology and measured to characterize geometric variation. According to the new extraction flow, interconnect technology file (ITF) has been optimized and established. As a result, both extracted error by layout parasitic extraction tool and simulated error by field solver have been improved obviously with this optimized ITF. Meanwhile, an on-chip interconnect test technique with nonoverlapping signal generation circuitry based on charge-induced-injection error-free charge-based capacitance measurement has been designed in this letter to simplify the test procedure.

A New Accurate and Fast Arithmetic for On-chip Spiral Inductors

A new simple and accurate arithmetic for the low frequency inductances of spiral inductors has been presented in this paper. It gets self-inductance by adding up each turns self-inductance and gets mutual inductance from a simplified equivalent model. The effectiveness and accuracy have been verified by HFSS8.0 simulation, the experiment measurements and other researchers published measurements. Compared with experiment measurements, the relative errors for this arithmetic are less than 4%. Compared with HFSS8.0 simulations, the relative errors are within 3%. So it is useful for the design and optimization of passive spiral inductors.

Air-Stable and Self-Driven Perovskite Photodiodes with High On/Off Ratio and Swift Photoresponse

Recent years have witnessed rapid developments in organic-inorganic hybrid perovskites, among which 2D Ruddlesden-Popper (RP) perovskites stand out due to their outstanding ambient stability. In photodetector applications, 2D RP perovskites are mostly limited to lateral device configuration because of their preferred in-plane charge transportation within quantum well structures. In this work, the low-temperature solution construction of 2D RP perovskite-based photodiodes in vertical device architecture is demonstrated. The paradigm phenylethylamine (PEA) spacer cation-based 2D perovskites are fabricated and optimized by exploiting a combination of a NH4 Cl additive and dimethyl sulfoxide solvent (DMSO) solvent. They show increased crystallinity, extended photoluminescence lifetimes, and importantly a generation of 3D phases embedded within 2D perovskites, which efficiently promotes charge transfer. As a result, the photodetectors exhibit a high on/off ratio up to 2 × 104 , a large photocurrent of 0.34 mA cm-2 , and rapid rise (5.8 ms) and decay time (4.6 ms). Of critical importance is the outstanding film/device stabilities demonstrated by storage in air (at 25 °C with 60% relative humidity) for 15 days as well as under UV illumination for 1.5 h and after 1500 bending cycles on flexible substrate.

Analytical long-term NBTI recovery model with slowing diffusivity and locking effect of hydrogen considered

Abstract The NBTI degradation caused by hole trapping in gate insulator process-related preexisting traps (∆ VHT) and in generated bulk insulator traps (∆ VOT) can recover in several seconds (< 10 s), whereas the long-term recovery is dominated by interface trap generation (∆ VIT). In this paper, various explanations of NBTI recovery have been reviewed and a compact analytical long-term NBTI recovery model in which the slowing down diffusivity and locking effect of H2 are involved has been derived. The triangular diffusion profile of H2 is approximated and the fitting coefficient ξ of slowing down diffusivity is related to the stress and recovery time. Our proposed model has been validated by the previous theories and numerical calculation. Moreover, the investigation of NBTI recovery on a 40-nm CMOS process has been experimentally carried out and the results show that our compact NBTI recovery model can describe the long-term recovery well.

A Novel Variation-Aware Interconnection Parasitic Extraction Method for 40nm Technology

In this paper, a novel technique is presented to perform variation-aware interconnection parasitic parameters extraction on 40nm process technology. Several kinds of test structure are designed for these extractions. Based on layouts of parasitic metal capacitors, 3D simulations are performed and typical Interconnection Technology Format (ITF) profile is extracted. Full mapping tests are made on these structures and distribution of measurements are analyzed. With the statistical data and process information attached, the statistical parameters are extracted using Principal Component Analysis Method. Finally, according to comparison of statistical data between simulations and measurements, the variation-aware ITF is proved accurate and necessary for the nano-scale IC process technology.

A novel structure of non-planar RF spiral inductor based on silicon

In this paper, a novel structure of non-planar inductor based on silicon is presented. The simulation plot of the magnetic distribution reveals that magnetic field reaches its maximum intensity near the inner turns of planar inductor, so it is necessary to deal with the peak value of the magnetic field in the centre of the inductor which causes great substrate loss. An extra layer of silicon dioxide under central several turns of the inductor is proposed in this novel design, and then the inductor becomes non-planar. The simulation results show this method can increase the peak Q factor by nearly 10%

Optimization of on-chip inductor and its application in low-pass filter

This paper presents the design of on-chip inductor employing Greenhouse theory. The electrical parameter of the inductor is converted to physical dimensions of the inductor by approximate algorithm, and vice versa. Based on the optimization of inductor, an equivalent circuit model of the low-pass filter (LPF) including substrate parasitics is proposed. The designed LPF is fabricated on high-resistivity silicon substrate in conventional CMOS process. Measurements on the three-pole maximally flat low-pass filter give -3dB bandwidth of 977MHz that is close to the nominal design value of 980MHz.