Zheng Ren

Optimization of BSIM3 I-V Model for Double Diffused Drain HV MOSFET

This paper presents a technique for modeling double diffused drain high-voltage MOSFET devices (DDD HV MOSFET). I-V measurements have been made by Agilent ICCAP. Based on the difference between DDD HV MOSFET and normal low voltage MOSFET devices (LV MOSFET), the Rd dependency of Vgs is discussed and equations of Rd and delta (the effective Vds parameter) in the BSIM3v3 model have been optimized. Three parameters are added: Prwg2 which is gate bias quadric coefficient of Rdsw and delta1, delta2 which are gate bias coefficients of delta. The optimization has been made on SPICE BSIM3v3 model using SPICE macro model. The contrast between I-V simulated data of optimized HV MOSFET model and the measured data has been made after parameters extraction. They fit very well

Extraction of geometry-related interconnect variation based on parasitic capacitance data

A new interconnect parasitic extraction flow considering geometry-related variation has been proposed in this letter. The 42 interconnect capacitance loads were fabricated by 55-nm process technology and measured to characterize geometric variation. According to the new extraction flow, interconnect technology file (ITF) has been optimized and established. As a result, both extracted error by layout parasitic extraction tool and simulated error by field solver have been improved obviously with this optimized ITF. Meanwhile, an on-chip interconnect test technique with nonoverlapping signal generation circuitry based on charge-induced-injection error-free charge-based capacitance measurement has been designed in this letter to simplify the test procedure.

PSP Statistical Modeling for 40nm MOSFET

This paper presents a statistical model based on PSP MOSFET model in 40nm CMOS technology. Nine parameters are modified in PSP model to establish the statistical model. The simulation result verifies the accuracy of the model, the error of σ value is controlled within 5% and the error of mean value within 2%. The proposed model could optimize the circuit design in nanometer CMOS technology node.

Poly Gate Proximity Effect Modeling for 40nm CMOS

A new compact and scalable psp model for the layout proximity effect of poly gate in 40nm CMOSFET is proposed. This model takes into account the impact of gate space and neighboring gates number on mobility and flatband voltage. With the silicon verification, saturation current change up to 5%–7% and flatband voltage change up to 6-8mv is modeled in the constructed model. Vthlin, Idlin and Gmmax are also monitored. These good results show the importance of the new model for circuit design in advanced CMOS node.

Simple and accurate radio frequency inductance expression for on-chip planar spiral inductors

A simple and accurate expression for calculating radio frequency (RF) inductance of square, hexagonal, octagonal and circular on-chip planar spiral inductors is presented in this paper. The expression presented shows a functional relationship between RF inductance (LRF) and some certain electrical parameters of inductors, which are low frequency inductance (L0), self resonant frequency (fR), work frequency (fW) and substrate material correlation coefficient (beta). Compared with both three-dimensional field solver simulation data and experiment data, the RF inductance data obtained by the presented expression matched both of them typically within around 5%. So it is worth expecting that this expression would be very useful for designing and optimizing of inductors, especially for applying inductors to RF ICs.

A Novel Variation-Aware Interconnection Parasitic Extraction Method for 40nm Technology

In this paper, a novel technique is presented to perform variation-aware interconnection parasitic parameters extraction on 40nm process technology. Several kinds of test structure are designed for these extractions. Based on layouts of parasitic metal capacitors, 3D simulations are performed and typical Interconnection Technology Format (ITF) profile is extracted. Full mapping tests are made on these structures and distribution of measurements are analyzed. With the statistical data and process information attached, the statistical parameters are extracted using Principal Component Analysis Method. Finally, according to comparison of statistical data between simulations and measurements, the variation-aware ITF is proved accurate and necessary for the nano-scale IC process technology.

A Novel Nano-Scale Multi-Finger MOSFET DC Model Parameters Extraction Method

A novel Nano-scale scalable multi-finger RF MOSFET model extraction method is presented in this paper. First, Parasitic resistances induced by measuring probe are analyzed, according to which the extraction method of parasitic probe resistor are proposed. Secondly, it is proved that stress effects on the MOS channel scale with finger number. Moreover, Based on experiment data, it is concluded that several MOS instances, finger numbers, channel width and length highly affect the parasitic source and drain resistance of Multi-finger MOS. An empirical scalable model on them has been suggested. A complete flow of model parameters extraction and optimization on nano-scale multi-finger MOSFET is presented.

Numerical analysis of pull-in voltage in contact MEMS switch with double actuated electrodes

This paper presents the numerical analysis of pull-in voltage for a contact MEMS switch with a couple of electrodes. The lumped-model for double actuated coupled parallel-plate actuators is applied to describe the pull-in phenomenon. And based on the pull-in analysis results, some optimizing approaches are developed to lower the pull-in voltage for a contact MEMS switch.

High-isolation contact switch in MEMS phase shifter

The design, fabrication and testing of high-isolation contact MEMS switch using AlSi membrane on high-resistivity silicon substrates are described. Simulation result of the switch is analyzed and shows good performance. The measured results show that the isolation of the MEMS switch is better than -30dB at 0.05 - 5GHz. And it has not only low actuation voltage, but also the high reliability. So this contact MEMS switch can be widely used in MEMS phase shifters.