Shounak Dhar

UTPlaceF: a routability-driven FPGA placer with physical and congestion aware packing

Field programmable gate array (FPGA) packing and placement without routability consideration could lead to unroutable results for high-utilization designs. Conventional FPGA packing and placement approaches are shown to have severe difficulties to yield good routability. In this paper, we propose an FPGA packing and placement engine called UTPlaceF that simultaneously optimizes wirelength and routability. A novel physical and congestion aware packing algorithm and a hierarchical detailed placement technique are proposed. UTPlaceF outperforms state-of-the-art FPGA placers simultaneously in runtime and solution quality on International Symposium on Physical Design (ISPD) 2016 benchmark suite. Compared with the top three winners of ISPD’16 FPGA placement contest, UTPlaceF can deliver 6.2%, 11.6%, and 29.1% better routed wirelength with shorter runtime.

Detailed placement for modern FPGAs using 2D dynamic programming

In this paper, we propose a 2-dimensional dynamic programming (DP) based detailed placement algorithm for modern FPGAs for wirelength and timing optimization. By tuning a control parameter, our algorithm can perform fast heuristic or exact optimization. Our algorithm further enables us to solve the single row placement problem optimally which was not possible with the previous DP approaches, while also reducing its complexity to Θ(p.N.2N) from the naive Θ(p.N!) (where p is the average degree of a net). Experiments on industrial-scale benchmarks show promising results.

An Effective Timing-Driven Detailed Placement Algorithm for FPGAs

In this paper, we propose a new timing-driven detailed placement technique for FPGAs based on optimizing critical paths. Our approach extends well beyond the previously known critical path optimization approaches and explores a significantly larger solution space. It is also complementary to single-net based timing optimization approaches. The new algorithm models the detailed placement improvement problem as a shortest path optimization problem, and optimizes the placement of all elements in the entire timing critical path simultaneously, while minimizing the costs of adjusting the placement of adjacent non-critical elements. Experimental results on industrial circuits using a modern FPGA device show an average placement clock frequency improvement of 4.5%.

Microresonator-based electro-optic full adder for optical computing in integrated photonics (Conference Presentation)

Due to the bottleneck in the continuation of Moore’s law as well as the drastically increasing trend of bandwidth, silicon photonics has emerged as the most promising candidate for implementing next-generation communication networks with ultralow power and ultrahigh speed. Recently, optical computing in integrated photonics, which outperforms electrical counterparts both in power consumption and bandwidth, has attracted a renewed interest due to the accessibility and maturity of ultracompact passive and active integrated components. However, up to now, most of relevant research about optical computing still focus on the realization of fundamental logic gates, not even close to feasible large-scale computing system. In this paper, we demonstrate a high-speed ripple-carry electro-optic full adder using micro-resonators. This approach adopts photons instead of electrons to realize logic operations as well as transfer carry signals from one bit to the next, while all the control signals of operands are applied simultaneously at and within every clock cycle. Thus, the severe latency issue that accumulates as the size of full adder increases can be circumvented, allowing for the improvement in computing speed. This approach also outperforms the conventional electrical counterpart in terms of power consumption due to the relatively smaller propagation loss and switching energy.

Comparison of microrings and microdisks for high-speed optical modulation in silicon photonics

The past several decades have witnessed the gradual transition from electrical to optical interconnects, ranging from long-haul telecommunication to chip-to-chip interconnects. As one type of key component in integrated optical interconnect and high-performance computing, optical modulators have been well developed these past few years, including ultrahigh-speed microring and microdisk modulators. In this paper, a comparison between microring and microdisk modulators is well analyzed in terms of dimensions, static and dynamic power consumption, and fabrication tolerance. The results show that microdisks have advantages over microrings in these aspects, which gives instructions to the chip design of high-density integrated systems for optical interconnects and optical computing.The past several decades have witnessed the gradual transition from electrical to optical interconnects, ranging from long-haul telecommunication to chip-to-chip interconnects. As one type of key component in integrated optical interconnect and high-performance computing, optical modulators have been well developed these past few years, including ultrahigh-speed microring and microdisk modulators. In this paper, a comparison between microring and microdisk modulators is well analyzed in terms of dimensions, static and dynamic power consumption, and fabrication tolerance. The results show that microdisks have advantages over microrings in these aspects, which gives instructions to the chip design of high-density integrated systems for optical interconnects and optical computing.

UTPlaceF 2.0: A High-Performance Clock-Aware FPGA Placement Engine

Modern field-programmable gate array (FPGA) devices contain complex clock architectures on top of configurable logics. Unlike application specific integrated circuits (ASICs), the physical structure of clock networks in an FPGA is pre-manufactured and cannot be adjusted to different applications. Furthermore, clock routing resources are typically limited for high-utilization designs. Consequently, clock architectures impose extra clock constraints and further complicate physical implementation tasks such as placement. Traditional ASIC placement techniques only optimize conventional design metrics such as wirelength, routability, power, and timing without clock legality consideration. It is imperative to have new techniques to honor clock constraints during placement for FPGAs. In this article, we propose a high-performance FPGA placement engine, UTPlaceF 2.0, that optimizes wirelength and routability while honoring complex clock constraints. Our proposed approaches consist of an iterative minimum-cost-flow-based cell assignment as well as a clock-aware packing for producing clock-legal yet high-quality placement solutions. UTPlaceF 2.0 won first place in the ISPD’17 clock-aware FPGA placement contest organized by Xilinx, outperforming the second- and the third-place winners by 4.0% and 10.0%, respectively, in routed wirelength with competitive runtime, on a set of industry benchmarks.

Nanophotonic devices for power-efficient computing and optical interconnects

To solve the problem in huge power consumption of the data centers and cloud computing, we design an extreme optical adder architecture suitable for ultra-high bit count. n-bit full adder are full implementable on a silicon platform using guided wave optics.