Mahesh A. Iyer

Identifying sequential redundancies without search

Previous solutions to the difficult problem of identifying sequential redundancy are either based on incorrect theoretical results, or rely an unrealistic simplifying assumptions, or are applicable only to small circuits. In this paper we show the limitations of the existing definitions of sequential redundancy and introduce a new concept of c-cycle redundancy as a generalization of the conventional notion of sequential redundancy. We present an efficient algorithm, FIRES, to identify c-cycle redundancies without search. FIRES does not assume the existence of a global reset nor does it require any state transition information. FIRES has provably polynomial-time complexity and is practical for large circuits. Experimental results on benchmark circuits indicate that FIRES identifies a large number of redundancies. We show that, in general, the redundant faults identified by FIRES are not easy targets for state-of-the-art sequential rest generators.

Wavefront technology mapping

The wavefront technology mapping algorithm leads to a very simple and efficient implementation that elegantly decouples pattern matching and covering but circumvents that patterns have to be stored for the entire network simultaneously. This coupled with dynamic decomposition enables trade-off of many more alternatives than in conventional mapping algorithms. The wavefront algorithm maps optimally for minimal delay on directed acyclic graphs (DAGs) when a gain based delay model is used. It is optimal with respect to the arrival times on each path in the network. A special timing mode for multi-source nets allows minimization of other (non-delay) metrics as a secondary objective while maintaining delay optimality.

Race a word-level atpg-based constraints solver system for smart random simulation

Functional verijication of complex designs largely relies on the use of simulation in conjunction high-level verijication languages (HVL) and test-bench automation (TBA) tools. In a constraints-based verification methodology, constraints are used to model the environmental restrictions of the Design Under Verification (DUV), and are specijied using HVL constructs. The job of a constraints solver is to produce multiple random solutions to these constraints. These random solutions are used to drive legal random stimulus to the DUV using procedural HVL constructs.

A robust solution to the timing convergence problem in high-performance design

Traditional ASIC design flows have treated logic synthesis and physical design as separate steps in the flow. A recent trend in design automation has been to integrate placement and logic synthesis operations for designs that strive for high performance. The motivation for this is ascribed to achieving timing convergence. These efforts attempt a brute-force combination of techniques from the two fields. We present an architecture for combining synthesis transforms with rough placement. There are three main contributions of this paper. First we present a system architecture that permits a clean separation of placement and synthesis issues and combines the two solutions in an elegant manner. Second, we propose a minor modification to the current ASIC design flow to enable timing convergence. Third, we use design rules for correct circuit operation to drive the placement and the synthesis components of the system. We present results for a set of high performance ASIC designs which demonstrate the practicality of our method.

Surprises in sequential redundancy identification

This paper addresses some misconceptions about redundancy in synchronous sequential circuits. We provide examples to illustrate the differences between untestability and redundancy and discuss existing techniques to identify sequential redundancy. We show that some of these methods are based on incorrect theoretical results. Specifically, we show that untestable faults in balanced pipeline circuits are not necessarily redundant, and that a constant function (i.e. a signal that is always 0 or 1 after initialization) does not always indicate a redundancy. We also show that adding a global reset mechanism or retiming synchronous circuitry may introduce redundancies.

High Time For High Level ATPG

Rohit Kapur, Synopsys, Inc. Matteo Sonza Reorda, Politecnico di Torino Christos A. Papachristou, Case Western Reserve University Scott Davidson, Sun Microsystems Wolfgang Roethig, NEC Electronics, Inc. ATPG for circuits described using hardware description languages was first proposed almost two decades ago. Since then, design has moved into RTL, and is heading for the behavioral level, while ATPG is still mired in a sea of gates. While ATPG is used widely for several CAD problems like ‘logic synthesis and static functional and timing verification, state-of-the-art ATPG for generating manufacturing test vectors is still performed after technology mapping. Logic design and physical design are also making good progress merging into each other, in an attempt to solve high performance issues like timing convergence, crosstalk, noise, etc. New sign-off design methodologies are also being proposed in this context. Some of the key requirements for an RTL test sign-off methodology would be to check for test design rules and automatically fix violations, enhance testability using DFT and other means, and generate manufacturing test vectors. Among these, high level ATPG seems like the most challenging problem. This panel examines why this is, and asks if this situation is likely to change.

A robust and scalable technique for the constraints solving problem in high-level verification

Constraints solving is an important problem in a random simulation-based functional verification methodology. Constraints are used to model the environmental restrictions of the design under verification and the job of the constraints solver is to produce multiple random solutions that satisfy the constraints. We present RACE, a new word-level ATPG-based system for solving combinational constraint expressions. RACE builds a high-level circuit model to represent the constraints and implements a branch-and-bound algorithm to solve them. Experimental results on industrial test cases demonstrate the effectiveness of RACE. RACE has been successfully used for random stimulus generation in the context of a commercial high-level test-bench automation tool with simulation for RTL verification.

On improving optimization effectiveness in interconnect-driven physical synthesis

In modern designs, the delay of a net can vary significantly depending on its routing. This large estimation error during the pre-routing stage can often mislead the optimization of the netlist. We extend state-of-the-art interconnect-driven physical synthesis by introducing a new paradigm (namely, persistence) that relies on guaranteed net routes for the most sensitive nets while performing circuit optimization in the pre-route stage. We implemented our proposed approach in a cutting-edge industrial physical synthesis flow; this involved the automatic identification and routing of critical nets that were likely to be mispredicted, the automatic update of their routes during the subsequent pre-routing stage optimizations, and the guaranteed retention of their routes across the routing stage. Our approach achieves significant performance improvements on a suite of real-world 65nm designs, while ensuring that the impact on their routability remains negligible. Furthermore, our experimental results scale very well with design size.