James E. Jaussi

A Scalable 5–15 Gbps, 14–75 mW Low-Power I/O Transceiver in 65 nm CMOS

We present a scalable low-power I/O transceiver in 65 nm CMOS, capable of 5-15 Gbps operation over single-board and backplane FR4 channels with power efficiencies between 2.8-6.5 mW/Gbps. Nonlinear power-performance tradeoff is achieved by the use of scalable transceiver circuit blocks and joint optimization of the supply voltage, bias currents and driver power with data rate. Low-power operation is enabled by passive equalization through inductive link termination, active continuous-time RX equalization, global TX/RX clock distribution with on-die transmission lines, and low-noise offset-calibrated receivers.

An 8Gb/s source-synchronous I/O link with adaptive receiver equalization, offset cancellation and clock deskew

An 8Gb/s binary source-synchronous I/O link with adaptive receiver-equalization, offset cancellation and clock deskew is implemented in 0.13/spl mu/m CMOS. The analog equalizer is implemented as an 8-way interleaved, 4-tap discrete-time linear filter. On-die adaptation logic determines optimal receiver settings.

Modeling and Analysis of High-Speed I/O Links

Improvements in signaling methods, circuits and process technology have allowed input/output (I/O) data rates to scale beyond 10 Gb/s over several legacy channels. In this regime, it is critical to accurately model and comprehend channel/circuit nonidealities in order to co-optimize the link architecture, circuits, and interconnect. Empirical and worst-case analysis methods used at lower rates are inadequate to account for several deterministic and random noise sources present in I/O links today. In this paper, we review models and methods for statistical signaling analysis of high-speed links, and also propose a new way to integrate behavioral modeling approaches with analytical methods. A computationally efficient segment-based analysis method is shown to accurately capture the effect of transmit jitter and its interaction with the channel. In addition, a new jitter interpretation approach is proposed to enable the analysis of arbitrary I/O clocking topologies. We also present some examples to illustrate the practical utility of these analysis methods in the realm of high-speed I/O design.

An 8-Gb/s simultaneous bidirectional link with on-die waveform capture

A full-duplex transceiver capable of 8-Gb/s data rates is implemented in 0.18-/spl mu/m CMOS. This equalized transceiver has been optimized for small area (329 /spl mu/m /spl times/ 395 /spl mu/m) and low power (158 mW) for point-to-point parallel links. Source-synchronous clocking and per-pin skew compensation eliminate coding bandwidth overhead and reduce latency, jitter, and complexity. This link is self-configuring through the use of automatic comparator offset trim and adaptive deskew. Comprehensive diagnostic capabilities have been integrated into the transceiver to provide link, interconnect, and circuit characterization without the use of external test equipment. With a resolution of 4 mV and 9 ps, these capabilities enable on-die eye diagram generation, equivalent time waveform capture, noise characterization, and jitter distribution measurements.

A 47

A 47 × 10 Gb/s chip-to-chip interface consuming 660 mW is demonstrated in 45 nm CMOS. The circuitry and interconnect are co-designed to minimize power and area for a wide parallel interface. Power is reduced by amortizing clocking, minimizing the span of clock signals and pairing a low-swing transmitter driver with a sensitive receiver sampler. The active silicon area is compressed by 64% relative to the C4 bumps using on-chip transmission line routing. A dense, top-side package connector and bridge enable both high off-chip interconnect density and low overall power by reducing equalization and deskew requirements. The interface also demonstrates fast power management for the I/O circuits. The receiver power can be reduced by 93% during standby and an integrated wake-up timer indicates that all lanes return reliably to active mode in <;5 ns. The interface operates at 470 Gb/s with an aggregate bit error ratio better than 2 ×10-18 while consuming 1.4 mW/Gb/s and occupies 3.2 mm2 active silicon area.

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We describe a DRAM interface operating at 3.6 Gb/s/pin implemented in 130-nm CMOS logic and 110-nm DRAM process technologies. It utilizes simultaneous bidirectional (SBD) signaling in a daisy-chained (repeated), point-to-point configuration to enable high performance scalable memory subsystems; and also provides direct attach capability for DRAMs to memory controllers or other logic devices. Source-synchronous strobes are used for data capture, minimizing strobe-to-data jitter. A low-jitter differential clock retimes the data at each DRAM on a per DIMM basis preventing jitter from accumulating in repeated data. The phase of this clock is adjusted on each DRAM to minimize the latency of the repeaters. 80 mW of total power is dissipated per DRAM I/O at 3.6 Gb/s. We present results from a system using both memory controller and DRAM repeater test chips.

10 Gb/s 1.4 mW/Gb/s Parallel Interface in 45 nm CMOS

High-aggregate bandwidth interfaces with minimized power, silicon area, cost and complexity will be essential to the viability of future microprocessor systems. Optimization of microprocessor interfaces at the system level is crucial to providing the most cost-effective and efficient solution. This paper details a comprehensive interconnect and system level analysis method that can be used to accurately evaluate platform-level tradeoffs and has been correlated to link measurements with 10% accuracy. System tradeoffs with respect to interconnect quality, equalization, modulation, clock architecture are shown. Interconnect and circuit density improvements are identified as a promising research direction to maximize the bandwidth and power efficiency of future microprocessor platforms.

A 3.6-Gb/s point-to-point heterogeneous-voltage-capable DRAM interface for capacity-scalable memory subsystems

Future microprocessor platforms will require system-level optimization of the I/O to minimize cost and maximize aggregate bandwidth. Critical parameters such as silicon area, power, testability, and off-chip interconnect quality must be properly balanced to maximize the I/O performance versus cost ratio. For example, there is a fundamental tradeoff between clock quality and equalizer effectiveness [1]. Producing precision RX and TX clocks and a sensitive RX may impact the power and area of some circuits, but it could allow the use of simple, low-power linear equalizers to minimize the overall link power. Additionally, these equalizers will become much more effective by limiting near-end crosstalk and stubbed backplane (BP) via length. To demonstrate this system-level optimization effort, we have developed a 20Gb/s forwarded clock I/O system intended for a wide parallel link with small area and low power.

Future Microprocessor Interfaces: Analysis, Design and Optimization

A general model for injection-locked LC oscillators (LC-ILOs) is presented that is valid for any tank quality factor and injection strength. Important properties of an ILO such as lock-range, phase shift, bandwidth and response to input jitter are described. An LC-ILO together with a half-rate data sampler is implemented as a forwarded-clock I/O receiver in 45-nm CMOS. A strongly-injected low-Q LC oscillator enables clock deskew across 1UI and rejects high-frequency clock jitter. The complete 27 Gb/s ILO-based data receiver has an overall power efficiency of 1.6 mW/Gb/s.

A 20Gb/s Forwarded Clock Transceiver in 90nm CMOS B.

This paper describes a method for both filtering and deskewing a link clock using a differential injection-locked LC-DCO and demonstrates a forwarded-clock data receiver using this technique operating at 27 Gb/s.