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Dive into the research topics where Shui-Bao Liang is active.

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Featured researches published by Shui-Bao Liang.


electronic components and technology conference | 2016

Phase Field Simulation of Segregation of the Bi-Riched Phase in Cu/Sn-Bi/Cu Solder Interconnects under Electric Current Stressing

Shui-Bao Liang; Chang-Bo Ke; Wen-Jing Ma; Min-Bo Zhou; Xin-Ping Zhang

The migration and segregation of Bi atoms in Cu/Sn-Bi/Cu solder interconnects under electric current stressing usually induce the formation of Bi-riched layers at the anode side, which can cause the failure of solder interconnects easily. In our study, the microstructure evolution of the eutectic Sn-Bi solder in a Cu/Sn-Bi/Cu flip chip solder joint and a right-angle Cu/Sn-Bi/Cu solder interconnect is simulated by phase field method. Further, the phase field equation is coupled with the Laplace equation governing the electric potential to simulate the segregation of the Bi-riched phase in Cu/Sn-Bi/Cu solder interconnects, in which the Bi-riched phase and Sn-riched phase inhomogeneously distribute. The coarsening behavior of the eutectic microstructure can also be seen in the simulation results, and the phases grow and become coarse along multiple directions in the flip chip solder interconnect compared with that in the right-angle solder interconnect. Under electric current stressing, Bi atoms migrate towards the anode side, while Sn atoms move in the opposite direction, and finally a segregated layer of Bi-riched phase is formed at the anode side, which is consistent with the experimental studies. The phase separation first occurs near the bottom corner of the right-angle solder interconnect. Moreover, the inhomogeneity of microstructures can influence the current density distribution, and the electromigration and segregation of the Bi-riched phase can induce the increase of both the voltage and resistance.


international conference on electronic packaging technology | 2015

Morphological evolution and migration behavior of the microvoid in Sn/Cu interconnects under electrical field studied by phase-field simulation

Shui-Bao Liang; Chang-Bo Ke; Min-Bo Zhou; Xin-Ping Zhang

Microvoids usually form at the interface between the Sn-based solder and Cu substrate during aging process. The existence and growth (electromigration and coalescence) of the microvoids can decrease the reliability of solder joints, in particular for the joints undergoing electrical current stressing of high density. In this paper, a diffuse interface model is employed to simulate the morphological evolution and migration behavior of microvoids in the solder interconnect consisting of the Sn-based solder and Cu substrate (i.e., Sn/Cu system), under electrical fields. Simulations take into account the coupled effect of surface diffusion and electrical field. The order parameter equation and electrical field equation are solved by using the finite difference method. The validity of this method is confirmed by the agreement of the evolution of noncircular microvoids driven by surface energy with that predicted theoretically. Simulation results show that the electrical field has significant influence on the morphological evolution of microvoids. The circular microvoids migrate from the region with high electric potential to the region with low potential under electrical field. Moreover, the migration velocity of the microvoid is constant. With increasing the voltage, the migration rate increases and under a high voltage the severe migration of microvoid may lead to a failure of the solder interconnect by the electromigration or coalescence of microvoids.


electronic components and technology conference | 2017

Microstructure Simulation and Thermo-Mechanical Behavior Analysis of Copper Filled Through Silicon Vias Using Coupled Phase Field and Finite Element Methods

Shui-Bao Liang; Chang-Bo Ke; Han-Jiang; Min-Bo Zhou; Xin-Ping Zhang

High thermo-mechanical stresses are usually induced in through silicon via (TSV) structures due to the mismatch of coefficients of thermal expansion (CTE) between copper and silicon in Cu filled TSVs, which has brought an increasing concern for the reliability problems during fabrication process and operation of electronic devices. The size, shape and orientation of Cu grains in TSVs and their effects on thermo-mechanical behavior of TSVs can not be ignored, especially with the continuous miniaturization and increasing integration of 3D ICs. In this study, the dynamic evolution characteristics of grain growth in a Cu filled TSV are simulated by a two-dimensional phase field model firstly, and then the thermo-mechanical behavior of the TSV with different grain morphologies under annealing condition is investigated by finite element method (FEM), and finally the interaction effects of grain growth and thermo-mechanical behavior in the TSV during operation of electronic devices are studied.


Microelectronics Reliability | 2017

Numerical simulations of migration and coalescence behavior of microvoids driven by diffusion and electric field in solder interconnects

Shui-Bao Liang; Chang-Bo Ke; Wen-Jing Ma; Min-Bo Zhou; Xin Ping Zhang

Abstract A diffuse interface model is developed to simulate the effect of electric field on the morphological evolution and migration behavior of the microvoid in the solder interconnect consisting of the Sn based solder and Cu substrate (i.e., Sn/Cu system). The model takes into account the coupled effect of surface diffusion and electric field, and the validity of the model is confirmed by good agreement between the simulation and theoretical predictions in terms of evolution behavior of the noncircular microvoid driven by surface energy. The results show that the coalescence of microvoids driven only by surface energy occurs when the microvoids contact each other. The evolution and migration of the microvoid under electric field are governed by the magnitude of electric field and the initial size of the microvoid. The microvoid migrates at a constant velocity under a weak electric field, while the strong electric field results in the shape change of the microvoid from circular to narrow crack-like. In addition, the migration velocity of the microvoid increases linearly with the voltage and is inversely proportional to the size of the microvoid; a small microvoid can catch up with a large one, and finally they merge to form a larger microvoid, which may promote the open circuit failure near the solder/Cu interface in solder interconnects.


international conference on electronic packaging technology | 2016

Phase field simulation of morphological evolution and migration of the microvoid in small scale solder interconnects driven by temperature gradient

Shui-Bao Liang; Chang-Bo Ke; Min-Bo Zhou; Xin-Ping Zhang

Thermomigration issue has attracted increasing attention as it can induce the failure of solder interconnects, owing to the migration of atoms driven by heat flux. Further, thermomigration can promote the formation of microvoids, and also induces the evolution and migration of many other types of microvoids in solder interconnects, resulting in loss of the integrity of solder interconnects and a dramatic decrease of the reliability, in particular for the solder interconnects under high temperature gradient. In this paper, a phase field model is developed and employed to simulate the evolution and migration behavior of microvoids in solder interconnects under the applied temperature gradient. Simulations take into account the coupled effect of surface diffusion and temperature gradient, and the feasibility and validity of this method are confirmed. The results show that for the solder interconnect containing an initially circular void in microscale, the microvoid migrates to the cold regions along the temperature gradient. In addition, under a higher temperature gradient, the microvoid migrates with higher speed and its shape becomes unstable, which will increase the potential of failure in solder interconnects. Moreover, the temperature gradient can drive two microvoids to migrate and coalesce to a large micorvoid, and eventually a slit-like void is formed. Finally, the microvoid migration kinetics is also investigated, and the result is consistent with the analytical solution.


international conference on electronic packaging technology | 2016

Phase field simulation of the microstructural evolution and electromigration-induced phase segregation in line-type Cu/Sn-Bi/Cu solder interconnects

Shui-Bao Liang; Chang-Bo Ke; Meng-Ying Tan; Min-Bo Zhou; Xin-Ping Zhang

The separation state and inhomogeneous nature of microstructure in Sn-Bi based solders can reduce the reliability of solder interconnects obviously. Notably, continuously scaling down of the feature size of solder interconnects may greatly promote the electromigation and segregation of Bi atoms in Cu/Sn-Bi/Cu interconnects under electric current stressing, which will induce the inhomogeneity of the microstructure and decrease the reliability of solder interconnects inevitably. In this study, a phase field model is developed to simulate the microstructure of the eutectic Sn-Bi solder in a line-type Cu/Sn-Bi/Cu interconnect. Further, the phase field equation is coupled with the Laplace equation governing the electric potential to simulate the segregation of the Bi-rich phase in line-type Cu/Sn-Bi/Cu interconnects under electric current stressing. The simulated evolution and coarsening behavior of the eutectic microstructure are consistent with experimental studies. Under electric current stressing, Bi atoms migrate towards the anode side, and finally a Bi-rich phase region forms at the anode side, while a Sn-rich phase layer forms at the cathode side. Moreover, by reversing the direction of electric current, the Bi-rich phase layer is formed at the anode side starts to dissolve, and finally a continues Bi-rich phase layer is formed on the opposite side.


international conference on electronic packaging technology | 2014

Phase field simulation of Kirkendall voids at the interface of microscale Sn/Cu system lead-free interconnects

Shui-Bao Liang; Chang-Bo Ke; Wen-Jing Ma; Min-Bo Zhou; Xin-Ping Zhang

During the soldering process, Kirkendall voids may form at the Cu/Cu3Sn interface and in Cu3Sn compound layer. Excessive formation and growth of Kirkendall voids may increase the potential for brittle interfacial fracture, and the existence of voids will reduce the thermal conductivity. Thus, characterization of formation and growth of Kirkendall voids is very important to the evaluation of performance and reliability of solder interconnects. In this paper, a phase field crystal model of a substitutional binary is developed and applied to simulate the formation and growth of Kirkendall voids in the Cu/Cu3Sn interface in the atomic scale. The simulation results show that the formation and growth of Kirkendall voids includes four stages: incubation, nucleation, growth and healing stages. With increasing the grain boundary angle, more Kirkendall voids may form and the average diameter of Kirkendall voids decreases due to the competitive growth between different Kirkendall voids.


international conference on electronic packaging technology | 2017

Coupled phase field and finite element modeling of void evolution and physical property change of micro flip-chip solder joints under electromigration and elastic stress field

Shui-Bao Liang; Chang-Bo Ke; Min-Bo Zhou; Xin-Ping Zhang

The formation and propagation of void in flip-chip solder joints would reduce the reliability of solder interconnects obviously. Notably, continuously scaling down of the feature size of solder joints may greatly promote the formation and propagation of void in solder joints under electric current stressing. In addition, the elastic stress field induced by the externally applied stress has a big influence on the void evolution, leading to a decrease of reliability of solder joints inevitably. In this study, a coupled phase field and finite element method is used to simulate and investigate the void formation and propagation in a flip-chip Sn/Cu solder joint under electric current stressing and tensile stress, with considering the atom diffusion driven by chemical potential gradient and electrical field induced by electric current stressing. The simulation results of evolution and propagation of the void are consistent with experimental studies. Under electric current stressing, the void forms at the entrance corner of the electron flow, and propagates to the anode side along the interface between the Sn solder matrix (ball) and copper pad. Moreover, simulation results show that the externally applied tensile stress can promote the void propagation and the acceleration of the increasing rate of the voltage in the solder joint under coupled loads of electric current stressing and tensile stress.


international conference on electronic packaging technology | 2017

Microstructure simulation and thermo-mechanical behavior analysis of Cu-filled through silicon vias (TSVs) using combined Monte Carlo and finite element method

Shui-Bao Liang; Cheng Wei; Chang-Bo Ke; Min-Bo Zhou; Xin-Ping Zhang

Grain characteristics of copper filler have an important influence on physical properties of through silicon vias (TSVs) in three-dimensional (3D) packaging. Due to the mismatch of coefficients of thermal expansion (CTE) between the copper and silicon, there exist obvious thermal stresses when the TSV structure is bearing thermal load. However, the elastic response characteristics of copper can be affected distinctly by the size, shape and orientation of copper grains in TSVs. These effects can not be ignored, especially for 3D ICs undergoing continuous miniaturization and increasing integration. In this study, the grain growth and evolution of a typical copper filler in the TSV structure is dynamically simulated and investigated by using Monte Carlo method (MCM), then the thermo-mechanical behavior of TSVs with considering the grain characteristics of copper filler is studied with combined MCM and finite element method (FEM), i.e., MC-FE method. Besides, the effects of grain evolution on the protrusion of copper filler in the TSV is also investigated. Simulation results are presented for providing more quantitative description and comprehensive understanding of the influences of microstructure evolution of copper filler on the thermo-mechanical behavior of Cu-filled TSVs.


Transactions of Nonferrous Metals Society of China | 2017

Morphological evolution and growth kinetics of Kirkendall voids in binary alloy system during deformation process—Phase field crystal simulation study

Wenjing Ma; Chang-bo Ke; Shui-Bao Liang; Min-Bo Zhou; Xin-Ping Zhang

The formation and growth of Kirkendall voids in a binary alloy system during deformation process were investigated by phase field crystal model. The simulation results show that Kirkendall voids nucleate preferentially at the interface, and the average size of the voids increases with both the time and strain rate. There is an obvious coalescence of the voids at a large strain rate when the deformation is applied along the interface under both constant and cyclic strain rate conditions. For the cyclic strain rate applied along the interface, the growth exponent of Kirkendall voids increases with increasing the strain rate when the strain rate is larger than 1.0×10−6, while it increases initially and then decreases when the strain rate is smaller than 9.0×10−7. The growth exponent of Kirkendall voids increases initially and then decreases gradually with increasing the length of cyclic period under a square-wave form constant strain rate.

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Min-Bo Zhou

South China University of Technology

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Xin-Ping Zhang

South China University of Technology

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Chang-Bo Ke

South China University of Technology

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Cheng Wei

South China University of Technology

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Wen-Jing Ma

South China University of Technology

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Chang-bo Ke

South China University of Technology

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Han Jiang

South China University of Technology

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Wenjing Ma

South China University of Technology

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Xin Ping Zhang

South China University of Technology

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Hui-Hui Yuwen

South China University of Technology

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