Shumpei Kawasaki

SH3: high code density, low power

Hitachis SH series microprocessors feature 32-bit RISC architecture with a 16-bit, fixed-length instruction set. We describe SH3, a pipelined implementation of the SH architecture with on-chip cache, MMU, and software-programmable power management. Its higher code density and corresponding improvement in instruction-fetch latency lead to higher performance than typical 32-bit RISC architectures achieve. These features, small die size, and low power consumption make SH3 an ideal microprocessor for portable computing systems or multimedia systems.

A floating-point VLSI chip for the TRON architecture: an architecture for reliable numerical programming

A description is given of the Gmicro/FPU (floating-point unit), a chip that provides floating-point instructions for both the Gmicro/200 and the Gmicro/300 microprocessors. The VLSI central-processing-unit architecture, for which it is designed, defines 23 coprocessor instructions, some of which are designed to be used in the floating-point instructions. Some background information is given, and the requirements, architecture, implementation, and evaluation of the Gmicro/FPU are discussed.<<ETX>>

Microprogrammable processor for object-oriented architecture

An advanced microprocessor has been developed for the high performance execution of object oriented language programs. In object oriented languages, improvement of frequent or complex operations such as dynamic type checking, procedure calls, and storage management, contributes toward the increase of overall performance. In order to improve their performance, the microprocessor adopts large on-chip register files, a large EPROM for microstore, and ingenious instruction dispatching and tag-handling mechanisms. By specially treating frequently accessed data, i.e., allocating activation records in register files, much of the data traffic can be effectively localized within the chip, and the complexity of procedure calls as well as the burden imposed on storage management can be alleviated. The tag-handling mechanisms efficiently perform dynamic type checking. As the result, the microprocessor, together with an efficient microprogram, executes object oriented language programs much faster than existing computers. Furthermore, it can efficiently execute other high-level languages by using corresponding microprograms, especially AI-languages.

A floating point processing unit for the Gmicro CPU

This paper describes the architecture and implementation of a newly developed floating point processing unit (FPU). It was developed as a high performance 32-bit coprocessor of the 32-bit Gmicro microprocessor, which satisfies the IEEE 754 Standard for Binary Floating-Point Arithmetic.