Shunichi Iwata

The approach to multiple instruction execution in the GMICRO/400 processor

This paper describes the instruction execution mechanism of the 32-bit microprocessor GMICRO/400 that executes more than one operation per clock cycle. The chip integrates a dual operation integer unit, a floating-point unit, an 8-Kbyte instruction cache, an 8-Kbyte data cache, and a 64-bit external data bus. The GMICRO/400 utilizes both superscalar and VLIW design techniques. The integer unit and the floating-point unit concurrently execute two integer and one floating-point instructions. The dual operation integer unit executes two operations in one clock cycle, under the control of a microprogram using long microinstruction words, when it executes a multiple-operation instruction.<<ETX>>

Performance evaluation of a microprocessor with on-chip DRAM and high bandwidth internal bus

The M32R/D is a 32-bit microprocessor with on-chip 2M-byte (16M-bit) DRAM. It has a 32-bit RISC CPU, 32-bit/spl times/16-bit multiply and accumulator, 2M-byte DRAM, 2K-byte cache memory, and a memory controller. The CPU, DRAM, and cache memory are connected with a 128-bit 66.6MHz internal bus. This wide internal bus allows high speed transfer of instructions. The use of a 128-bit bus resulted in a 13% improvement in performance as compared with 32-bit bus.

A 32-bit microprocessor with high performance bit-map manipulation instructions

The GMICRO/100, a 32-b microprocessor based on the TRON architecture specification, is described. The GMICRO/100 uses high-level instructions, such as those in bit-map manipulation. The bit-map instructions are implemented by pipelining micro-operations, and achieve optimum use of the memory bus in the execution. The bit-map instructions are 2 to 3 times faster than repeating move instructions by the software. Microprogram development tools for the GMICRO/100 design are described.<<ETX>>