Sugako Otani

Heterogeneous Multicore SoC With SiP for Secure Multimedia Applications

A heterogeneous multicore system-on-chip (SoC) has been developed for high-definition (HD) multimedia applications that require secure DRM (digital rights management). The SoC integrates three types of processors: two specific-purpose accelerators for cipher and high-resolution video decoding; one general-purpose accelerator (MX); and three CPUs. This is how our SoC achieves high performance and low power consumption with hardware customized for video processing applications that process a large amount of data. To achieve secure data control, hardware memory management and software system virtualization are adopted. The security of the system is the result of the cooperation between the hardware and software on the system. Furthermore, a highly tamper-resistant system is provided on our SiP (System in a package), through DDR2 SDRAMs and a flash memory that contain confidential information in one package. This secure multimedia processor provides a solution to protect contents and to safely deliver secure sensitive information when processing billing transactions that involve digital content delivery. The SoC was implemented in a 90 nm generic CMOS technology.

Peach: A Multicore Communication System on Chip with PCI Express

The PCI Express Adaptive Communication Hub (Peach) is an eight-core communication system on chip with four PCI Express Revision 2.0 ports, each with four lanes. Peach realizes a high-performance, power-aware, highly dependable network that uses PCI Express not only for connecting peripheral devices but also as a communication link between computing nodes. This approach opens up new possibilities for a range of communications.

An 80Gb/s dependable communication SoC with PCI express I/F and 8 CPUs

InfiniBand is widely used as a low-latency and high-bandwidth network for highperformance computing (HPC) clusters [1]. However, power consumption and system cost become large in exchange for high performance on small-scale clusters or embedded systems. To cope with these problems, we use PCI Express (PCIe) [2] technology as a direct communication link between computing nodes. Point-to-point bidirectional packet communication is implemented by using PCIe basic operations such as memory read/write between the host and the device. Therefore, PCIe technology can be applied to inter-node communication and thereby eliminate communication overhead and extra power consumption caused by the protocol conversion via the network device [3].

An 80 Gbps dependable multicore communication SoC with PCI express I/F and intelligent interrupt controller

An 80 Gbps dependable communication SoC with four 4X PCIe Rev.2.0 ports has been developed that acts as a communication link with high transfer capability. By using the PCIe I/F, the SoC can address two computing nodes as peers, breaking the traditional PCIe limit of only linking to a single master processor. The SoC also employs an intelligent ICU that supports an initiate data transfer function and offloads interrupt services from the CPUs. This function can dramatically reduce processing time by 20% compared to using CPU interrupt handlers. To achieve a highly dependable network, the multicore processor continuously monitors the network status and operates the fault handling efficiently by using IRQ affinity. Our SoC achieves the power consumption of 3.2W at 80 Gbps and the power efficiency of 0.04 W/Gbps, which is 51.5% more power efficiency than 4X InfiniBand.

Software architecture of a secure multimedia system using a multicore SoC and software virtualization

This paper presents a secure multimedia system using a multicore system-on-chip (SoC) and software system virtualization. This secure multimedia system provides a solution to protect contents and to safely deliver secure sensitive information when processing billing transactions that involve digital content delivery.

Heterogeneous multicore SoC for secure multimedia applications

A heterogeneous multicore SoC (System on a Chip) has been developed for HD (high-definition) multimedia applications that require secure DRM (digital rights management). The SoC integrates three types of processors: two specific-purpose accelerators for a cipher and a high-resolution video decoding; one general-purpose accelerator (MX: Matrix processor); and three CPUs. This is how our SoC achieves high performance and low power consumption with hardware customized for video processing applications that process a large amount of data. To achieve secure data control, hardware memory management and software system virtualization are adopted. The security of the system is the result of the cooperation between the hardware and software on the system. Furthermore, a highly tamper-resistant system is provided on our SiP (system in a package), through DDR memories and Flash ROM that contain confidential information in one package. This secure multimedia processor provides a solution to protect contents and to safely deliver secure sensitive information when processing billing transactions that involve digital content delivery. The SoC was implemented in the 90 nm generic CMOS technology.

3.5 A 40nm flash microcontroller with 0.80µs field-oriented-control intelligent motor timer and functional safety system for next-generation EV/HEV

Electric Vehicle / Hybrid-Electric Vehicle (EV/HEV) technologies are becoming increasingly important for realizing fuel-efficient vehicles. In particular, maximizing the energy efficiency of motors, while enhancing power and speed requires high-performance semiconductor devices, such as microcontrollers (MCU) and power devices. However, high-performance MCUs suitable for EV/HEV applications have yet to be reported, while attractive power devices, such as SiC devices, are becoming commonplace [1]. In this paper, we have designed an MCU architecture with intelligent motor-timer system (IMTS), including 0.8µs high-speed field-oriented-control (FOC) processing and an angle-tuning circuit (ATC). We have also designed a functional safety mechanism essential for automotive use [2].

RXv2 processor core for low-power microcontrollers

We have developed a new processor architecture for microcontrollers which integrate high-capacity FLASH memory and many peripheral functional modules. This paper describes processor core architecture for low-power microcontrollers and our approach for reducing energy consumption with instruction fetch mechanisms. A large fraction of the total power budget of the microcontroller is the energy consumption in the path from the FLASH memory to the processor. An enhanced instruction set and pipeline structure provide an effective balance between high code density, power consumption performance and high processing performance with an novel prefetching unit to reduce the number of memory accesses.