Shunsuke Koshihara

Automated CD-SEM recipe creation: a new paradigm in CD-SEM utilization

As the trends in integrated circuit fabrication follow Moores Law to smaller feature sizes, one trend seen in lithographic technology is the continually increasing use of optical enhancements such as Optical Proximity Correction (OPC). Small size perturbations are designed into the nominal feature shapes on the reticle such that the intended shape is printed. Verifying the success of OPC is critical to ramp-up and production of new process technologies. CD-SEMs are imaging tools which are capable of measuring feature sizes in any part of a chip, either in a test structure or within a circuit. A new trend in CD-SEM utilization is the implementation of automated recipe generation of complex CD-SEM recipes. The DesignGauge system uses design-to-SEM recipe creation and data collection. Once the recipe creation flow is implemented, the task of recipe creation can be accomplished within minutes. These applications enable a CD-SEM to be utilized to collect data for very complex OPC CD-SEM recipe runs which measure many different unique linewidths, spaces, and pattern placements within a circuit to check OPC success and lithographic fidelity. The data collection can provide accurate data results that can be utilized for comparing achieved feature measurements to nominal values from the design layout. This new application adds much value to the CD-SEM compared to other technologies such as OCD, as it completes the evaluation of in-circuit behavior to test structures in a scribe lane, something OCD currently cannot do. The present work evaluates the capabilities of DesignGauge, which is available for the latest-generation Hitachi S-9380II CD-SEMs. The evaluation includes rigorous tests of navigation, pattern recognition success rates, SEM image placement, throughput of recipe creation and recipe execution.

Enabling CD SEM metrology for 5nm technology node and beyond

The CD SEM (Critical Dimension Scanning Electron Microscope) is one of the main tools used to estimate Critical Dimension (CD) in semiconductor manufacturing nowadays, but, as all metrology tools, it will face considerable challenges to keep up with the requirements of the future technology nodes. The root causes of these challenges are not uniquely related to the shrinking CD values, as one might expect, but to the increase in complexity of the devices in terms of morphology and chemical composition as well. In fact, complicated threedimensional device architectures, high aspect ratio features, and wide variety of materials are some of the unavoidable characteristics of the future metrology nodes. This means that, beside an improvement in resolution, it is critical to develop a CD SEM metrology capable of satisfying the specific needs of the devices of the nodes to come, needs that sometimes will have to be addressed through dramatic changes in approach with respect to traditional CD SEM metrology. In this paper, we report on the development of advanced CD SEM metrology at imec on a variety of device platform and processes, for both logic and memories. We discuss newly developed approaches for standard, IIIV, and germanium FinFETs (Fin Field Effect Transistors), for lateral and vertical nanowires (NW), 3D NAND (three-dimensional NAND), STT-MRAM (Spin Transfer Magnetic Torque Random-Access Memory), and ReRAM (Resistive Random Access Memory). Applications for both front-end of line (FEOL) and back-end of line (BEOL) are developed. In terms of process, S/D Epi (Source Drain Epitaxy), SAQP (Self-Aligned Quadruple Patterning), DSA (Dynamic Self-Assembly), and EUVL (Extreme Ultraviolet Lithography) have been used. The work reported here has been performed on Hitachi CG5000, CG6300, and CV5000. In terms of logic, we discuss here the S/D epi defect classification, the metrology optimization for STI (Shallow Trench Isolation) Ge FinFETs, the defectivity of III-V STI FinFETs,, metrology for vertical and horizontal NWs. With respect to memory, we discuss a STT-RAM statistical CD analysis and its comparison to electrical performance, ReRAM metrology for VMCO (Vacancy-modulated conductive oxide) with comparison with electrical performance, 3D NAND ONO (Oxide Nitride Oxide) thickness measurements. In addition, we report on 3D morphological reconstruction using CD SEM in conjunction with FIB (Focused Ion Beam), on optimized BKM (Best Known Methods) development methodologies, and on CD SEM overlay. The large variety of results reported here gives a clear overview of the creative effort put in place to ensure that the critical potential of CD SEM metrology tools is fully enabled for the 5nm node and beyond.

Line width roughness accuracy analysis during pattern transfer in self-aligned quadruple patterning process

Line edge roughness (LER) and line width roughness (LWR) are analyzed during pattern transfer in a self-aligned quadruple patterning (SAQP) process. This patterning process leads to a final pitch of 22.5nm, relevant for N7/N5 technologies. Measurements performed by CD SEM (Critical Dimension Scanning Electron Microscope) using different settings in terms of averaging, field of view, and pixel size are compared with reference metrology performed by planar TEM and three-Dimensional Atomic Force Microscope (3D AFM) for each patterning process step in order to investigate the optimal condition for an in-line LWR characterization. Pattern wiggling is als0 quantitatively analyzed during LER/LWR transfer in the SAQP process.

Improvement of optical proximity-effect correction model accuracy by hybrid optical proximity-effect correction modeling and shrink correction technique for 10-nm node process

Abstract. The model accuracy of optical proximity-effect correction (OPC) was investigated by two modeling methods for a 10-nm node process. The first method is to use contours of two-dimensional structures extracted from critical dimension-scanning electron microscope (CD-SEM) images combined with conventional CDs of one-dimensional structures. The accuracy of this hybrid OPC model was compared with that of a conventional OPC model, which was created with only CD data, in terms of root-mean-square (RMS) error for metal and contact layers of 10-nm node logic devices. Results showed improvement of model accuracy with the use of hybrid OPC modeling by 23% for contact layer and 18% for metal layer, respectively. The second method is to apply a correction technique for resist shrinkage caused by CD-SEM measurement to extracted contours for improving OPC model accuracy. The accuracy of OPC model with shrink correction was compared with that without shrink correction, and total RMS error was decreased by 12% by using the shrink correction technique. It can be concluded that the use of CD-SEM contours and the shrink correction of contours are effective to improve the accuracy of OPC model for the 10-nm node process.

Prospects for using primary electron-based CD metrology

CD SEM’s used for CD Metrology in semiconductor fabs rely upon secondary electron emission to indirectly image features on process wafers. The use of secondary electrons by current CD SEM technology limits the resolution of this metrology and hinders its ability to meet future requirements. An idea that has garnered some interest from both the research and commercial sectors is to use backscattered, or primary, electrons with very low energy losses to image patterned features directly. Such a device would operate with acceleration (and landing) potentials in the range of 50 keV-200 keV. One concern is whether the high energy incident electrons will damage active devices. It has been hypothesized that the substrate’s reduced stopping power for high energy electrons will result in the majority of the electron energy being deposited far below the device structures. We have explored the issue of device damage from high energy and high dose incident electrons and find that this technique results in unacceptable transistor degradation at all of the doses and landing energies explored. We present our findings in this paper.

The need for LWR metrology standardization: the imec roughness protocol

As semiconductor technology keeps moving forward, undeterred by the many challenges ahead, one specific deliverable is capturing the attention of many experts in the field: Line Width Roughness (LWR) specifications are expected to be less than 2nm in the near term, and to drop below 1nm in just a few years. This is a daunting challenge and engineers throughout the industry are trying to meet these targets using every means at their disposal. However, although current efforts are surely admirable, we believe they are not enough. The fact is that a specification has a meaning only if there is an agreed methodology to verify if the criterion is met or not. Such a standardization is critical in any field of science and technology and the question that we need to ask ourselves today is whether we have a standardized LWR metrology or not. In other words, if a single reference sample were provided, would everyone measuring it get reasonably comparable results? We came to realize that this is not the case and that the observed spread in the results throughout the industry is quite large. In our opinion, this makes the comparison of LWR data among institutions, or to a specification, very difficult. In this paper, we report the spread of measured LWR data across the semiconductor industry. We investigate the impact of image acquisition, measurement algorithm, and frequency analysis parameters on LWR metrology. We review critically some of the International Technology Roadmap for Semiconductors (ITRS) metrology guidelines (such as measurement box length larger than 2μm and the need to correct for SEM noise). We compare the SEM roughness results to AFM measurements. Finally, we propose a standardized LWR measurement protocol - the imec Roughness Protocol (iRP) - intended to ensure that every time LWR measurements are compared (from various sources or to specifications), the comparison is sensible and sound. We deeply believe that the industry is at a point where it is imperative to guarantee that when talking about a critical parameter such like LWR, everyone speaks the same language, which is not currently the case.

Methodology for determining critical dimension scanning electron microscope measurement condition of sub-20 nm resist patterns for 0.33 NA extreme ultraviolet lithography

Abstract. A methodology to determine the optimum measurement condition of extreme ultraviolet (EUV) resist patterns in a critical dimension scanning electron microscope has been established. Along with many parameters that need to be optimized simultaneously, there are conflicting requirements of small resist shrinkage and high measurement precision. To overcome these difficulties, we have developed a methodology for ArF resist patterns from shrinkages and precisions predicted by the Taguchi method. In this study, we examined the extendibility of the methodology to sub-20 nm EUV resist patterns. The predicted shrinkage by the Taguchi method for an 18 nm EUV resist pattern showed a large prediction error due to its different dependence on acceleration voltage from ArF, so we used the shrinkage curve to predict shrinkage instead of the Taguchi method, as shrinkage depends only on irradiated electron dose. In contrast, precision can be predicted well by the Taguchi method as with ArF. We propose a methodology that consists of separate prediction procedures for shrinkage and precision using the shrinkage curve and Taguchi method, respectively. The proposed method was applied to an 18-nm EUV resist pattern. The optimum measurement condition with shrinkage of 1.5 nm and precision of 0.12 nm was determined.

CD-SEM utility with double patterning

Requirements for increasingly integrated metrology solutions continue to drive applications that incorporate process characterization tools, as well as the ability to improve metrology production capability and cycle time, with a single application. All of the most critical device layers today, and even non-critical layers, now require optical proximity correction (OPC), which must be rigorously modeled and calibrated as part of process development and extensively verified once new product reticles are released using critical dimension-scanning electron microscopy (CD-SEM) tools. Automatic setup of complex recipes is one of the major trends in CD-SEM applications, which is adding much value to CD-SEM metrology. In addition, as integrated circuit dimensions and pitches continue to shrink, double patterning (DP) has become more common. Thus automatic recipe setup has needed to incorporate capabilities to deal simultaneously with two layers. This has the benefit of allowing the user to measure the two different CD populations and the image shift in the lithography (i.e., the overlay). Thus automatic recipe creation can be used to characterize the DP pattern for both CD and overlay. DesignGauge, the automatic recipe utility for Hitachi CG series CD-SEMs, is not only capable of offline recipe creation, but also can also directly transfer design-based recipes into standard CD-SEM recipes for use with DP processes. These recipes can be used for OPC model-building and verification as with previous DesignGauge applications. The software also provides design template-based recipe setup for production layer recipes, which improves production tool utilization, as production recipes can thus be written offline for new products, improving first silicon cycle time, engineering time to generate recipes, and CD-SEM utilization. Another benefit of the application is that recipes are more robust than with conventional direct image-based pattern recognition. This paper explores the feasibility of matching a two-layer GDS pattern to features in an image, allowing for the more complex measurements involved in DP characterization. This work will evaluate DesignGauge with double litho double etch (DLDE DP), including rigorous tests of navigation, pattern recognition success rates, SEM image placement, throughput of the recipe creation, recipe execution, and verification of proper measurements of the dual CD populations and overlay.

CD-SEM tool stability and tool-to-tool matching management using image sharpness monitor

As device feature size reduction continues, requirements for Critical Dimension (CD) metrology tools are becoming stricter. For sub-32 nm node, it is important to establish a CD-SEM tool management system with higher sensitivity for tool fluctuation and short Turn around Time (TAT). We have developed a new image sharpness monitoring method, PG monitor. The key feature of this monitoring method is the quantification of tool-induced image sharpness deterioration. The image sharpness index is calculated by a convolution method of image sharpness deterioration function caused by SEM optics feature. The sensitivity of this methodology was tested by the alteration of the beam diameter using astigmatism. PG monitor result can be related to the beam diameter variation that causes CD variation through image sharpness. PG monitor can detect the slight image sharpness change that cannot be noticed by engineers visual check. Furthermore, PG monitor was applied to tool matching and long-term stability monitoring for multiple tools. As a result, PG monitor was found to have sufficient sensitivity to CD variation in tool matching and long-term stability assessment. The investigation showed that PG monitor can detect CD variation equivalent to ~ 0.1 nm. The CD-SEM tool management system using PG monitor is effective for CD metrology in production.

Advanced defect definition methods using design data

As Moores Law indicates, pattern feature sizes have become smaller and smaller, increasing the need for more critical metrology and inspection methodologies in integrated circuit fabrication. Critical methodologies are especially required in the inspection area where more critical defect definition methods are needed for the accurate evaluation of inspection tools. In traditional defect definition, we have to use only normal CD measurement results with manual measurement methods. This one dimensional definition method gives only defect size information which is not enough information to do accurate evaluation. In addition, there is a lot of measurement uncertainty such as human errors, measurement errors, and systematic errors which are included in the data of manual measurement methods. Because of these mentioned issues, evaluation results will differ from person to person and other environmental influences. In this paper, the defects will be defined not only with one dimensional measurement but also with two dimensional measurements using such functions as Gap measurement and EPE (Edge Placement Error) measurement in DesignGauge using Design Data. For example, misplacement defects in which a pattern is shifted on the wafer as shown in figure 1 below; traditional one dimension measurement methods can not detect this type of defect. However, with DesignGauge, misplacement defects can easily be detected if the Design Data is used as shown in figure 2. EPE measurement method, which is one of the advanced features of DesignGauge, will accurately define misplacement defects. As the trends of smaller feature sizes in integrated circuit fabrication continues, various defects should be controlled and measured with advanced defect definition methods using Design Data.