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Dive into the research topics where Shuroku Sakurada is active.

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Featured researches published by Shuroku Sakurada.


IEEE Transactions on Electron Devices | 1984

Ultrahigh-voltage high-current gate turn-off thyristors

Tsutomu Yatsuo; Takahiro Nagano; Hiroshi Fukui; Masahiro Okamura; Shuroku Sakurada

High-power GTOs with ratings of 2500 V . 2000 A have been developed, and a 4500 V . 2000 A GTO was trial fabricated and performance tested, for use in traction motor control equipment. Their low ON-state voltage was attained by applying a unique anode emitter shorting structure which does not require doping of a lifetime killer such as gold to obtain suitable GTO characteristics. Their high interrupt current was obtained by introducing a ring-shaped gate structure which has uniform operation between many segments in the devices during turn-off process.


international electron devices meeting | 1988

A new buried-gate GTO structure having a large safe operating area

Yukimasa Satou; Tsutomu Yatsuo; Shuroku Sakurada

A novel structure of a buried-gate GTO (gate turn-off thyristor) was proposed for expanding the safe operating area (SOA) of unit-GTOs. The SOA of unit-GTOs in a test sample GTO and the spike voltage at the limit of turn-off of the test sample were investigated experimentally. The SOA was calculated by means of a simple model in order to study the mechanism of the expansion of SOA in the structure. The SOA was expanded due to the reduction of the sheet resistance of the p-base layer by the fine mesh pattern of the buried layer. Corresponding to the increased size of the SOA, the spike voltage increased to 1000 V. >


Japanese Journal of Applied Physics | 1999

Investigation of Low Loss and High Reliability Encapsulation Technology in Large-Area, High-Power Semiconductor Devices

Toshiaki Morita; Mitsuo Kato; Jin Onuki; Hidekatsu Onose; Nobuyoshi Matsuura; Shuroku Sakurada

In order to realize uniform and low contact resistance in the low mounting force region for large-area, high-power semiconductor devices, the effects of hardness and surface cleanliness of metal sheets inserted between an Al cathode and Mo internal electrode on the contact resistance were investigated as a function of mounting force. Contact resistance was lowered with increasing cleanliness and decreasing hardness of the inserted sheet for all values of the mounting force. A new process was developed in which an Ag-plated Mo sheet is heat-treated at 573 K for 15 min in air. It was confirmed that devices with the new Ag-plated Mo sheet have efficient long form reliability. The contact resistance and its dependence on the mounting force of the devices using this sheet are of the same level as those of an Ag-sputtered Mo sheet and an Ag sheet.


Archive | 1986

Pressure contact semiconductor device

Shigeyasu Kouzuchi; Shuroku Sakurada; Tadashi Sakaue; Masafumi Ono


Archive | 1981

Gate turn-off thyristor with selective anode penetrating shorts

Takahiro Nagano; Isamu Sanpei; Shuroku Sakurada; Masaru Nakagawa


Archive | 1995

Semiconductor device and package structure therefore and power inverter having semiconductor device

Hidekatsu Onose; Shuroku Sakurada


Archive | 1980

Semiconductor device with double moat and double channel stoppers

Shuroku Sakurada; Yoichi Nakashima; Isao Kojima; Hideyuki Yagi; Tadaaki Kariya; Masayoshi Sugiyama


Archive | 1980

Semiconductor device having a high breakdown voltage

Shuroku Sakurada; Yoichi Nakashima; Isao Kojima; Hideyuki Yagi; Tadaaki Kariya; Masayoshi Sugiyama


Archive | 1985

Gate turn-off thyristor with integral capacitive anode

Shuroku Sakurada; Yasuhiko Ikeda


Archive | 1987

Gate turn-off thyristor of multi-emitter type

Toshihide Ujihara; Shuroku Sakurada; Tadashi Sakaue; Shuji Musha

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