Shuyu Bao

Fabrication and characterization of germanium-on-insulator through epitaxy, bonding, and layer transfer

A scalable method to fabricate germanium on insulator (GOI) substrate through epitaxy, bonding, and layer transfer is reported. The germanium (Ge) epitaxial film is grown directly on a silicon (Si) (001) donor wafer using a “three-step growth” approach in a reduced pressure chemical vapour deposition. The Ge epilayer is then bonded and transferred to another Si (001) wafer to form the GOI substrate. The Ge epilayer on GOI substrate has higher tensile strain (from 0.20% to 0.35%) and rougher surface (2.28 times rougher) compared to the Ge epilayer before transferring (i.e., Ge on Si wafer). This is because the misfit dislocations which are initially hidden along the Ge/Si interface are now flipped over and exposed on the top surface. These misfit dislocations can be removed by either chemical mechanical polishing or annealing. As a result, the Ge epilayer with low threading dislocations density level and surface roughness could be realized.

Integration of III–V materials and Si-CMOS through double layer transfer process

A method to integrate III–V compound semiconductor and SOI-CMOS on a common Si substrate is demonstrated. The SOI-CMOS layer is temporarily bonded on a Si handle wafer. Another III–V/Si substrate is then bonded to the SOI-CMOS containing handle wafer. Finally, the handle wafer is released to realize the SOI-CMOS on III–V/Si hybrid structure on a common substrate. Through this method, high temperature III–V materials growth can be completed without the presence of the temperature sensitive CMOS layer, hence damage to the CMOS layer is avoided.

Reduction of threading dislocation density in Ge/Si using a heavily As-doped Ge seed layer

High quality germanium (Ge) epitaxial film is grown directly on silicon (001) substrate with 6° off-cut using a heavily arsenic (As) doped Ge seed layer. The growth steps consists of (i) growth of a heavily As-doped Ge seed layer at low temperature (LT, at 400 °C), (ii) Ge growth with As gradually reduced to zero at high temperature (HT, at 650 °C), (iii) pure Ge growth at HT. This is followed by thermal cyclic annealing in hydrogen at temperature ranging from 600 to 850 °C. Analytical characterization have shown that the Ge epitaxial film with a thickness of ∼1.5 µm experiences thermally induced tensile strain of 0.20% with a treading dislocation density (TDD) of mid 106/cm2 which is one order of magnitude lower than the control group without As doping and surface roughness of 0.37 nm. The reduction in TDD is due to the enhancement in velocity of dislocations in an As-doped Ge film.

Defects reduction of Ge epitaxial film in a germanium-on-insulator wafer by annealing in oxygen ambient

A method to remove the misfit dislocations and reduce the threading dislocations density (TDD) in the germanium (Ge) epilayer growth on a silicon (Si) substrate is presented. The Ge epitaxial film is grown directly on the Si (001) donor wafer using a “three-step growth” approach in a reduced pressure chemical vapour deposition. The Ge epilayer is then bonded and transferred to another Si (001) handle wafer to form a germanium-on-insulator (GOI) substrate. The misfit dislocations, which are initially hidden along the Ge/Si interface, are now accessible from the top surface. These misfit dislocations are then removed by annealing the GOI substrate. After the annealing, the TDD of the Ge epilayer can be reduced by at least two orders of magnitude to <5 × 106 cm−2.

Germanium-on-silicon nitride waveguides for mid-infrared integrated photonics

A germanium-based platform with a large core-clad index contrast, germanium-on-silicon nitride waveguide, is demonstrated at mid-infrared wavelength. Simulations are performed to verify the feasibility of this structure. This structure is realized by first bonding a silicon-nitride-deposited germanium-on-silicon donor wafer onto a silicon substrate wafer, followed by the layer transfer approach to obtain germanium-on-silicon nitride structure, which is scalable to all wafer sizes. The misfit dislocations which initially form along the interface between germanium/silicon can be removed by chemical mechanical polishing after layer transfer process resulting in a high-quality germanium layer. At the mid-infrared wavelength of 3.8 μm, the germanium-on-silicon nitride waveguide has a propagation loss of 3.35 ± 0.5 dB/cm and a bend loss of 0.14 ± 0.01 dB/bend for a radius of 5 μm for the transverse-electric mode.

Integration of GaAs, GaN, and Si-CMOS on a common 200 mm Si substrate through multilayer transfer process

The integration of III–V semiconductors (e.g., GaAs and GaN) and silicon-on-insulator (SOI)-CMOS on a 200 mm Si substrate is demonstrated. The SOI-CMOS donor wafer is temporarily bonded on a Si handle wafer and thinned down. A second GaAs/Ge/Si substrate is then bonded to the SOI-CMOS-containing handle wafer. After that, the Si from the GaAs/Ge/Si substrate is removed. The GaN/Si substrate is then bonded to the SOI–GaAs/Ge-containing handle wafer. Finally, the handle wafer is released to realize the SOI–GaAs/Ge/GaN/Si hybrid structure on a Si substrate. By this method, the functionalities of the materials used can be combined on a single Si platform.

GeSn-on-insulator substrate formed by direct wafer bonding

GeSn-on-insulator (GeSnOI) on Silicon (Si) substrate was realized using direct wafer bonding technique. This process involves the growth of Ge1-xSnx layer on a first Si (001) substrate (donor wafer) followed by the deposition of SiO2 on Ge1-xSnx, the bonding of the donor wafer to a second Si (001) substrate (handle wafer), and removal of the Si donor wafer. The GeSnOI material quality is investigated using high-resolution transmission electron microscopy, high-resolution X-ray diffraction (HRXRD), atomic-force microscopy, Raman spectroscopy, and spectroscopic ellipsometry. The Ge1-xSnx layer on GeSnOI substrate has a surface roughness of 1.90 nm, which is higher than that of the original Ge1-xSnx epilayer before transfer (surface roughness is 0.528 nm). The compressive strain of the Ge1-xSnx film in the GeSnOI is as low as 0.10% as confirmed using HRXRD and Raman spectroscopy.

Low-threshold optically pumped lasing in highly strained germanium nanowires

The integration of efficient, miniaturized group IV lasers into CMOS architecture holds the key to the realization of fully functional photonic-integrated circuits. Despite several years of progress, however, all group IV lasers reported to date exhibit impractically high thresholds owing to their unfavourable bandstructures. Highly strained germanium with its fundamentally altered bandstructure has emerged as a potential low-threshold gain medium, but there has yet to be a successful demonstration of lasing from this seemingly promising material system. Here we demonstrate a low-threshold, compact group IV laser that employs a germanium nanowire under a 1.6% uniaxial tensile strain as the gain medium. The amplified material gain in strained germanium can sufficiently overcome optical losses at 83 K, thus allowing the observation of multimode lasing with an optical pumping threshold density of ~3.0 kW cm−2. Our demonstration opens new possibilities for group IV lasers for photonic-integrated circuits.Integrating group IV lasing devices into technologically relevant CMOS architectures has proven challenging. Here, the authors demonstrate low-threshold lasing, which is important for potential electronic and photonic circuits, using strained germanium nanowires as the gain material.

Monolithic integration of III–V HEMT and Si-CMOS through TSV-less 3D wafer stacking

III-V compound semiconductor HEMT integrated with silicon CMOS on a silicon common substrate is promising to open up new circuit applications and capabilities. In the conventional hybrid approach, silicon and III-V circuits are fabricated and packaged separately, and then assembled on a carrier substrate. This approach is confronted by interconnect size and losses, which affect performance, form factor, power consumption, cost, and complexity. For III/V-Si hybrid integration, direct epitaxial growth of III-V compounds on Si substrate or CMOS devices would be the most desirable approach, but the high temperature III-V materials growth would severely degrade the CMOS transistors. 3D wafer stacking combining bonding and layer transfer, on the other hand, is another promising approach to integrate III-V materials on Si substrate. In this work, 3D wafer stacking is used to integrate III-V and silicon on a common platform to realize a novel side-by-side hybrid circuit without the need for through silicon via (TSV). Integration of III-V materials (InGaAs and GaN) and SOI-CMOS on a common 200 mm Si substrate is demonstrated. The SOI-CMOS layer is temporarily bonded on a Si handle wafer. Another III-V/Si substrate is then bonded to the SOI-CMOS containing handle wafer. Oxide to oxide bonding is used as a bonding medium in this case. Various oxide to oxide bonding combinations (e.g. thermal oxide bond to PECVD SiO2 and PECVD SiO2 bond to PECVD SiO2) will be discussed and the counter-measures will be implemented. Post-bonding annealing of the bonded wafer pair is carried out at 300 °C in an atmospheric N2 ambient for 3 hours to further enhance the bond strength to > 1200 mJ/cm2. Finally, a void free SOI-CMOS on III-V/Si hybrid structure on a common substrate can be realized after the handle wafer is released.

The first GeSn FinFET on a novel GeSnOI substrate achieving lowest S of 79 mV/decade and record high Gm, int of 807 μS/μm for GeSn P-FETs

The worlds first GeSn p-FinFETs formed on a novel GeSn-on-insulator (GeSnOI) substrate is reported, with channel lengths L<inf>ch</inf> down to 50 nm and fin width W<inf>Fin</inf> down to 20 nm. In comparison with other reported GeSn p-FETs, record low S of 79 mV/decade, record high G<inf>m, int</inf>, of 807 μS/um (VDs of −0.5 V), and the highest G<inf>m, int</inf>/S<inf>sat</inf>, were achieved. The highest high-field hole mobility of 208 cm2/Vs (at inversion carrier density of 8×10⁻² cm⁻²) for GeSn p-FETs with CVD grown GeSn channel was also obtained.