Shuze Zhao

Burst-Mode Resonant LLC Converter for an LED Luminaire With Integrated Visible Light Communication for Smart Buildings

This study presents a digitally controlled LLC resonant dc-dc converter targeted to white LED luminaires in smart buildings. The module uses the LED array both for ambient lighting and for transmitting sensor data. Visible light communication is implemented with minimal incremental cost, by operating the LLC converter in burst mode, without causing any visible disturbance. The converter operates with a regulated average LED current, while the burst pulse timing is controlled to minimize the current disturbance and reduce the output capacitance. Variable pulse position modulation is used to modulate the data, while supporting a range of dimming settings. A digital demodulation scheme that supports variable frequency transmission is demonstrated. The 80 W, 340-400 to 23 V converter prototype has an efficiency of 95.1%. The bit error rate of the complete system is fully characterized versus distance and angle.

A dimmable LED driver for visible light communication (VLC) based on LLC resonant DC-DC converter operating in burst mode

The main focus of this work is the integration of the communication and power management functions of a 80W smart LED module. The luminair provides high-efficiency programmable ambient lighting and can also act as a networked sensor node to gather a variety of local measurements, which leads to improved safety, comfort and efficiency in future lighting systems. A dimmable LED driver based on the LLC resonant dc-dc converter topology is proposed to implement an emerging communication scheme, Visible Light Communication (VLC). VLC capitalizes on the high switching-speed of LEDs and offers several compelling advantages over conventional RF and wired communication schemes. The digitally controlled LLC converter operates in constant-current burst mode, where the burst is sequenced to independently control the dimming and transmission the data using the Variable Pulse Position Modulation (VPPM) protocol. A receiver circuit is designed to demodulate and decode the visible light signal. The 50 kb/s system is successfully demonstrated on a 308 LED Luminair with a digitally controlled LLC dc-dc converter.

Measure twice and cut once: Robust dynamic voltage scaling for FPGAs

Although dynamic voltage scaling (DVS) is a popular power reduction solution that has been widely used by processors and ASICs, it is still not commercially adopted by FPGAs. A unique feature of FPGAs that leads to challenges in adopting DVS is that the critical path and hence the minimum safe Vdd depends on the configured application. We present a robust DVS technique that solves these challenges. For each application, we generate a calibration table (CT) that stores the actual failing points of that application on a specific FPGA, under various operating conditions. This CT is used to scale Vdd while the application is running to guarantee safe operation with minimal power consumption. We develop an automated tool (FRoC) that ensures a Fast-Robust-Calibration of the FPGA to any application using it. FRoC ensures that the calibration process is invisible to FPGA users and does not add any extra manual steps to the design process. We show that our proposed DVS technique achieves a 33% total power reduction on two large applications.

A universal self-calibrating Dynamic Voltage and Frequency Scaling (DVFS) scheme with thermal compensation for energy savings in FPGAs

Field Programmable Gate Arrays (FPGAs) are widely used in telecom, medical, military and cloud computing applications. Unlike in microprocessors, the routing and critical path delay of FPGAs is user dependent. The design tool suggests a maximum operating frequency based on the worst-case timing analysis of the critical paths at a fixed nominal voltage, which usually means there is significant voltage or frequency margin in a typical chip. This paper presents a universal offline self-calibration scheme, which automatically finds the FPGA frequency and core voltage operating limit at different self-imposed temperatures by monitoring design-specific critical paths. These operating points are stored in a calibration table and used to dynamically adjust the frequency and core voltage according to the FPGA temperature when the application circuit is running. The self-calibration process is demonstrated on an Altera Cyclone IV 65-nm FPGA with a digitally controlled dc-dc converter, leading to 40% power savings in a typical digital filter application.

Server power management with integrated Lithium-Ion Ultracapacitor and bi-directional DC-DC converter for distributed UPS and reactive power mitigation

With the rapid proliferation of cloud computing, the cooling cost of large data centers and the reactive power impact on the grid have become a major concern. This paper presents an improved power architecture for servers with integrated energy storage. Lithium-Ion Ultracapacitors (LIC) are used to provide short-term UPS functionality, while also reducing the reactive power. The control scheme forces the PFC module to operate only in the region of high efficiency and high power factor during dynamic workloads. When the server is operating in idle mode, the PFC module draws only 12% less reactive power compared to having all four CPU cores operating at 100% load, which provides a strong incentive for the proposed scheme. A 200 kHz bi-directional multi-phase dc-dc converter operating in Hysteretic Current Mode Control (HCMC) is demonstrated to interface the 12 V internal bus with the LICs and the server load.

Failsafe smart LED module with thermal management, string current balancing and commutation for lifetime extension

A new LED driver architecture is presented for increasing the lifetime and reliability of solid-state lighting modules. The architecture targets indoor/outdoor industrial applications, where the overhead cost of a smart LED driver is outweighed by the added value of improved lifetime and fault tolerance. The system includes two complete sets of white LEDs and associated current-mode drivers. The digitally controlled dc-dc converters communicate with each-other to smoothly transfer current from one set of LEDs to another at a regular commutation interval. A low-power pulse-frequency-modulation mode is used to conserve power in the LED set that is off. The redundancy is also exploited to perform precise current balancing and health monitoring of the individual LED strings, while the total light output remains constant at all times. The architecture is demonstrated on a 25 W module with 154 white LEDs, which forms 1/4 of a full luminaire.

A DLL/PLL based multi-phase interleaved DC-DC converter with digital off-time control and active series balancing for electric vehicles

In this paper, a Delay-Locked Loop (DLL) and Phase Locked Loop (PLL) interleaving control scheme is demonstrated for multi-phase dc-dc converters in a light electric vehicle (LEV) application. Three interleaved non-inverting buck-boost (NIBB) sub-converters operate in peak current mode control (PCMC), and a fully digital off-time generator (OTG) is used in lieu of slope compensation for more accurate battery current sensing and improved converter dynamics. A DLL adjusts the master sub-converter off-time to maintain quasi fixed-frequency operation, while a PLL adjusts the two slave sub-converter off-times to achieve inductor current interleaving. Active series balancing is achieved by adding a single switch to the NIBB that connects to the adjacent series battery. The modified topology reuses the NIBB inductor to reduce system cost, complexity and weight, while providing balancing capabilities. The series balancing scheme is validated in simulation, and the DLL/PLL interleaving control schemes are demonstrated experimentally on a 12 V, 270 W dc-dc converter running at 555 kHz. With the DLL and PLL based frequency control, multi-phase dc-dc converter interleaving is achieved within 150 μs, and stable QFF operation and interleaving are maintained through step-up and step-down transient events.

A robust dynamic voltage scaling scheme for FPGAs with IR drop compensation

Dynamic Voltage Scaling (DVS) has been shown to yield dramatic power savings in modern FPGAs. Because each user-specific hardware design has unique critical paths, the hardware reconfigurability of FPGAs renders the implementation of DVS much more challenging compared to CPUs. A promising FPGA DVS scheme relies on a two-step, offline self-characterization of the minimum supply voltage of the critical paths versus frequency and temperature. It does not, however, account for the resistive voltage drops in the power distribution network during regular operation. As a result, voltage guard-bands are necessary, reducing the power savings. In this paper, a self-calibration method is demonstrated to directly measure the on-chip voltage using a calibrated Delay-Line ADC (DL-ADC). The temperature dependent resistance between the dc-dc converter feedback point and the on-chip critical path is accurately extracted and used in regular DVS mode to compensate the voltage drop according to the load current. The new DVS scheme is demonstrated on an Altera Cyclone IV 60-nm FPGA with a digitally controlled dc-dc converter.

Find the real speed limit: FPGA CAD for chip-specific application delay measurement

Process variation is increasing with each successive technology node, and it has reached the point where the worst-case timing modelling employed by current FPGA CAD tools is significantly underutilizing the available silicon. Previous studies have proposed exploiting FPGA reconfigurability to reduce this underutilization using techniques such as late binding and dynamic voltage scaling. Most of the proposed solutions require the ability to measure the target applications delay on each configured chip. To accurately measure the delay of an application on a certain chip, we must measure the delay of its speed limiting paths on this specific chip. In this paper, we present a variation-aware CAD tool that automatically generates calibration bitstreams to measure the delay of any input application. Our tool identifies the statistically critical paths of the circuit and optimally selects which paths to test such that it minimizes the chances of reporting an optimistic delay, under a constraint on the number of allowed calibration bitstreams. Experimental results across a suite of benchmarks show that with one calibration bitstream we achieve 16× lower probability of reporting an optimistic delay compared to a greedy approach. With three calibration bitstreams, we reduce the probability of optimism to two chips in a million, approximately 6,000 × lower than a greedy approach.