Olivier Trescases

A General Approach for Quantifying the Benefit of Distributed Power Electronics for Fine Grained MPPT in Photovoltaic Applications Using 3-D Modeling

This paper deals with photovoltaic power installations in urban environments. A general simulation method is developed to quantify the total energy yield for photovoltaic (PV) installation sites exploiting different levels of Distributed Maximum Power Point Tracking (DMPPT) granularity. The process includes 3-D modeling, shading evaluation of the installation site, and irradiance calculations on the PV surfaces on an hourly basis throughout the year. Three leading microconverter topologies are analyzed and the cost/performance tradeoff is discussed for panel-level DMPPT. The energy yield evaluation technique is confirmed by means of several miniature PV acquisition units for frequent irradiance and temperature measurements in the installation site. The yearly energy yield benefit is shown to be highly dependent on the relative shading in the three installation sites. It is found that the energy yield benefit easily outweighs the power electronics costs in two of the three installations for panel-level DMPPT. The analysis method can be used by PV installers and system designers for accurate energy yield prediction, as well as power electronics engineers who need to bound the cost of their design based on the net energy benefit of the installed PV system.

Predictive Algorithm for Optimizing Power Flow in Hybrid Ultracapacitor/Battery Storage Systems for Light Electric Vehicles

This study deals with the optimal control of hybrid energy storage systems for electric vehicle applications. These storage systems can capitalize on the high specific energy of Lithium-Ion batteries and the high specific power of modern ultracapacitors. The new predictive algorithm uses a state-based approach inspired by power systems optimization, organized as a probability-weighted Markov process to predict future load demands. Decisions on power sharing are made in real time, based on the predictions and probabilities of state trajectories along with associated system losses. Detailed simulations comparing various power sharing algorithms are presented, along with converter-level simulations presenting the response characteristics of power sharing scenarios. The full hybrid storage system along with the mechanical drivetrain is implemented and validated experimentally on a 500 W, 50 V system with a programmable drive cycle having a strong regenerative component. It is experimentally shown that the hybrid energy storage system runs more efficiently and captures the excess regenerative energy that is otherwise dissipated in the mechanical brakes due to the batterys limited charge current capability.

Digitally Controlled Current-Mode DC–DC Converter IC

The main focus of this paper is the implementation of mixed-signal peak current mode control in low-power dc-dc converters for portable applications. A DAC is used to link the digital voltage loop compensator to the analog peak current mode loop. Conventional DAC architectures, such as flash or ΔΣ are not suitable due to excessive power consumption and limited bandwidth of the reconstruction filter, respectively. The charge-pump based DAC (CP-DAC) used in this work has relatively poor linearity compared to more expensive DAC topologies; however, this can be tolerated since the linearity has a minor effect on the converter dynamics as long as the limit-cycle conditions are met. The CP-DAC has a guaranteed monotonic behavior from the digital current command to the peak inductor current, which is essential for maintaining stability. A buck converter IC, which was fabricated in a 0.18 μm CMOS process with 5 V compatible transistors, achieves a response time of 4 μs at fs=3 MHz and Vout=1 V, for a 200 mA load-step. The active area of the controller is only 0.077 mm2, and the total controller current-draw, which is heavily dominated by the on-chip senseFET current-sensor, is below 250 μA for a load current of Iout=50 mA.

A Digitally Controlled DC-DC Converter Module with a Segmented Output Stage for Optimized Efficiency

This paper presents a 4 MHz, 0.9 W digitally controlled DC-DC converter with a miniature planar inductor for 1.8 V portable devices. In applications such as cellular phones, it is crucial to achieve high conversion efficiency over the entire load range. A binary-weighted segmented power stage is used to dynamically optimize the converter efficiency by reducing the gate-drive losses at mid-to-light loads. An all-digital segment controller based on a load current estimator is demonstrated. This approach is most effective in the mid-load range, where the losses are reduced by 33 %, corresponding to an efficiency improvement of 7.5 % at Vin = 4.2 V. A peak efficiency of 89 % is achieved at fs = 4 MHz and Vin = 2.7 V

DC-DC converter for high granularity, sub-string MPPT in photovoltaic applications using a virtual-parallel connection

This paper focuses on fine-grained, sub-string MPPT in photovoltaic applications. An accurate energy forecasting analysis using 3D modeling of an urban PV installation site is used to show that performing MPPT at the sub-string level inside the panel can result in a substantial increase in the yearly energy yield. The virtual-parallel concept is used to exploit the robustness of parallel-connected PV modules to irradiance mismatches, while maintaining the wiring advantages of the physical series configuration. A power-efficient 300 kHz dc-dc converter prototype with three asymmetrical phases is implemented to demonstrate the benefits of DMPPT with substring voltage equalization within the panel. A variable interleaving scheme is used to reduce the output voltage ripple during shading conditions, which increases the output capacitor lifetime and improves the system reliability. The prototype is measured with a single PV panel under a variety of shading test cases to confirm the power benefit of the two auxiliary phases, which reaches up to 30%.

An EMI Reduction Technique for Digitally Controlled SMPS

A spread spectrum technique and system for reducing average electromagnetic interference (EMI) in low-power digitally controlled dc-dc switch-mode power supplies (SMPS) are introduced. The technique utilizes very simple hardware, where the switching frequency of a SMPS is dynamically varied over a controlled range. This is achieved by changing the supply voltage of a ring-oscillator based digital pulse-width modulator in a pseudo-random fashion, through 128 discrete steps. The change is performed with a 1-b DeltaSigma digital-to-analog converter. Compensator design guidelines for this variable frequency system are provided for obtaining good dynamic response. The technique was tested with a 500-mW, 1.8-V buck converter prototype, whose switching frequency was varied from 1.74 to 2.84 MHz. A reduction of 23 dB in the conducted EMI with an efficiency degradation of less than 0.1 % was obtained, compared to fixed frequency operation.

Predictive Efficiency Optimization for DC–DC Converters With Highly Dynamic Digital Loads

This paper presents a novel technique and system for increasing the efficiency of dc-dc converters that supply dynamic electronic loads, such as modern audio and video equipment and other devices whose power consumption largely depends on the digital data they process. The optimization does not require a current-measurement circuit and is well-suited to portable applications. It is based on a real-time prediction of the dc-dc converter output current from easily accessible digital data streams present in the targeted loads. The result of the prediction is used for dynamic adjustment of the power-stage transistor size and/or for switching into pulse-frequency-mode of output voltage regulation, in order to maximize the instantaneous converter efficiency on-the-fly. The use of a segmented power-stage allows the effective power-transistor size to be changed on-the-fly, and the tradeoff between the gate-drive and rms conduction losses is continuously optimized over the full range of operation. The effectiveness of the optimization is demonstrated on an experimental system, including a 1-W digitally controlled 4-MHz, 3.6 V-1.8 V buck converter with an integrated segmented power-stage and a digital high-fidelity class-D audio amplifier acting as the digital load. The results show a good agreement between the digitally predicted and actual dc-dc converter load current, as well as a reduction in total energy consumption of up to 38%.

A Segmented Digital Pulse Width Modulator with Self-Calibration for Low-Power SMPS

The next-generation, digitally controlled DC-DC converters require a high frequency, high resolution, low power and area efficient digital pulse width modulator (DPWM). This paper introduces a self-calibrated segmented DPWM that uses a delay-locked loop to calibrate adjacent delay segments. An 8-bit prototype designed in a 0.13-μm CMOS process operates at a switching frequency of 11.6 MHz, draws 190μA from a 1.2 V supply and occupies only 0.0075 mm2.

A low-power mixed-signal current-mode DC-DC converter using a one-bit /spl Delta//spl Sigma/ DAC

This work describes a dual-mode mixed-signal peak current-mode controller for high-frequency DC-DC converters. The simple controller provides peak-current protection, inherent low audio susceptibility, and is suitable for portable applications. The voltage feedback loop is implemented using a windowed ADC and a digital PI compensator based on lookup tables. The analog current command used in traditional current-mode controllers is generated by a 2nd order one-bit /spl Delta//spl Sigma/ DAC. The dual-mode controller automatically adjusts the DAC sampling frequency based on the digital error signal magnitude. The mixed-signal control strategy is experimentally verified on a 5V-to-1.5V 1 MHz buck converter prototype that exhibits a settling time of under 50 /spl mu/s.

Variable output, soft-switching DC/DC converter for VLSI dynamic voltage scaling power supply applications

The implementation of a low-voltage zero-voltage-switching quasi-square-wave (ZVS-QSW) buck converter capable of meeting the future challenges of low-voltage VRMs is presented. By eliminating switching losses, high-efficiency operation at switching frequencies beyond 1 MHz is achieved. The design uses novel high-speed dead-time-locked-loops with fast dead-time error rejection to ensure zero-voltage-switching under dynamic loads and variable output conditions. The ZVS-QSW converter, which was implemented in a mixed-signal 0.18 m CMOS process, has a measured efficiency of 82% at 5 MHz with a 1.4 V output. The ZVS-QSW converter is intended to supply the next generation VLSI chips with a variable supply voltage for dynamic voltage scaling (DVS) applications. DVS refers to the real-time scaling of the supply voltage to the VLSI chip to minimize dynamic power consumption, while satisfying a variable target clock frequency. Several DVS strategies are examined, and it is shown that DVS can be applied to the ZVS-QSW converter using a dual-mode configuration. An experimental DVS test-bench was developed using a state-of-the-art Xilinx CPLD capable of operating from 1.35 V to 1.8 V. The PID controlled DVS system achieves the maximum V/sub DD/ transition in 22 /spl mu/s.