Si-Ming Chiou

A Novel Coaxial-Structured Amorphous-Silicon p-i-n Solar Cell With Al-Doped ZnO Nanowires

A novel coaxial-structured amorphous-silicon (a-Si) p-i-n solar cell with 1-μm-long low-temperature hydrothermally synthesized Al-doped-ZnO (AZO) nanowires was demonstrated for the first time. The conversion efficiency η increased from 3.92% to 4.27% when the intrinsic a-Si thickness was increased from 25 to 150 nm and then decreased to 3.66% when the intrinsic layer thickness was further increased to 250 nm. It was attributed to an excessively thick intrinsic a-Si layer that would decrease the internal electrical field and interfere with charge separation. With the optimum intrinsic a-Si thickness of 150 nm, the conversion efficiency increased from 4.27% to 4.73% when the AZO wire length was increased from 1 to 2 μm. Moreover, the proposed coaxial-structured solar cell exhibited a nearly 46% efficiency enhancement over a conventional a-Si thin-film solar cell.

Superior Reliability of Gate-All-Around Polycrystalline Silicon Thin-Film Transistors with Vacuum Cavities Next to Gate Oxide Edges

The electrical characteristics and reliability of n-type gate-all-around (GAA) polycrystalline silicon thin-film transistors (poly-Si TFTs) with vacuum cavities next to the gate oxide edges are investigated. This novel structure is successfully fabricated by spacer formation, partial wet etching of a gate oxide, and in situ vacuum encapsulation. The electrical characteristics of the GAA poly-Si TFTs with vacuum cavities are superior to those of traditional GAA poly-Si TFTs because the vacuum cavity serves as an offset region to decrease the leakage current in the OFF state and as a field-induced drain (FID) to sustain the on-current in the ON state. In addition, regardless of whether static or dynamic electrical stress is imposed on these devices, the GAA poly-Si TFTs with vacuum cavities exhibit superior reliability to traditional ones owing to the simultaneous reduction of vertical and lateral electric fields near the drain junction during bias stressing due to the greater equivalent gate oxide thickness on the gate electrode edges.

Coaxial-Structured Solar Cells with Silicon Nanostructures

Coaxial-structured solar cells with different lengths silicon nanowires (SiNWs) fabricated by e-beam lithography and transformer coupled plasma reactive ion etching (TCP-RIE) were demonstrated in this paper. With the intrinsic amorphous silicon thickness of 15 nm and n-layer thickness of 25 nm, the shortcurrent density and the conversion efficiency of the flat film solar cell were 17.58 mA/cm and 3.16 %, respectively. Furthermore, the short-current density increased from 20.75 to 27.90 mA/cm and the conversion efficiency increased from 3.59 to 4.69 % when the silicon nanowires length was increased from 0.5 to 1 μm. The proposed coaxial-structured solar cells with SiNWs exhibited nearly 48.42 % efficiency enhancement over the plat film solar cell.

P1–2: A novel poly-Si TFTs with vacuum cavity next to the gate-oxide edge

Poly-Si TFTs with vacuum cavity next to the gate-oxide edge (quasi T-gate TFTs) have been fabricated with the wet-etching of gate-oxide and in-situ vacuum encapsulation techniques. The device characteristics of the quasi T-gate TFTs are examined and better than those of conventional TFTs, resulting from the vacuum cavity as the offset region to reduce the leakage current and as the field-induced drain (FID) to maintain the on-current. Furthermore, owing to the simultaneous reduction of the vertical and lateral electric field near the drain as bias stressing, the quasi T-gate TFTs achieve superior reliability than conventional ones.

The Instability of n-type LTPS TFTs Alternately operated in OFF region with drain biased

The instability characteristics of n-type low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) which are dynamically stressed in the OFF region with drain biased is investigated. Through the gate dynamically stressed in the OFF state with negative drain dc bias, the degradation mechanism of TFTs could be clarified and the defects are mainly generated in the source region. The higher the gate pulse frequency is, the more the TFTs devices degrade. A degradation model is proposed to explain the degradation mechanism of LTPS TFTs, according to three electrical measuring items, including the sampling currents, saturation forward & reverse I–V (FR-IV) transfer curves and C–V curves.

Turn-Around Phenomenon in the Degradation Trend of n-Type Low-Temperature Polycrystalline Silicon Thin-Film Transistors under DC Bias Stress

In this research, the instability of n-type low-temperature polycrystalline silicon (poly-Si) thin-film transistors (LTPS TFTs) is investigated under DC bias stress and a unique phenomenon is observed. At a large gate stressing voltage and simultaneous low to moderate drain biasing voltages operating in a linear region, a turn-around phenomenon is observed in the on-current (Ion) degradation trend of the TFT characteristics, resulting from the increase in maximum transconductance (Gm,max). However, under a larger drain stressing voltage, the turn-around phenomenon of the Ion degradation trend is observed to disappear owing to the extensive increases in threshold voltage (Vth) and trap state density (Ntrap) in a channel, which cause the TFTs to deteriorate monotonically.