Tsung-Kuei Kang

A novel LTPS-TFT-based charge-trapping memory device with field-enhanced nanowire structure

A novel gate-all-around low-temperature poly-Si (LTPS) thin-film transistor (TFT) silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory with field-enhanced nanowire (FEN) structure has been proposed to improve the program and erase (P/E) performance. Each nanowire inherently had three sharp corners fabricated simply by sidewall spacer formation to obtain high local electric fields. The field-enhanced carrier tunneling via such a structure led to faster P/E speed and wider memory window for the FEN-TFT SONOS as compared to the conventional planar (CP) counterpart. The improvement was also further verified with the simulation results. Such a high-performance FEN-TFT SONOS memory with process simplicity is very suitable for future system-on-panel (SOP) applications.

Gate-All-Around Poly-Si TFTs With Single-Crystal-Like Nanowire Channels

The gate-all-around (GAA) poly-Si thin-film transistors (TFTs) with single-crystal-like nanowire (NW) channels (SCLNCs) are demonstrated and characterized. Via the nanoscale nitride spacer, the Si NW can be easily transformed within one crystalline grain of the two-shot sequential-lateral-solidification poly-Si film. As compared with the planar ones, the GAA-SCLNC TFTs showed more excellent characteristics. The results clearly show that the variations of device characteristics can be reduced by increasing the numbers of NWs in the channels and an average mobility above 410 cm2/V·s with a low standard deviation can be achieved for the GAA-SCLNC TFTs with 20-NW channels.

High-Performance Single-Crystal-Like Nanowire Poly-Si TFTs With Spacer Patterning Technique

In this letter, high-performance single-crystal-like nanowire poly-Si TFTs with simple spacer patterning technique were demonstrated and characterized. Due to the nanoscale dimension formed by spacer patterning technique, each nanowire is easily transformed within one crystalline grain of the standard sequential-lateral-solidification (SLS) poly-Si film with the regularly arranged grains and thus performed with a single-crystal like device channel. Due to the high-crystallinity channel, together with the tri-gated structure, the fabricated devices revealed good device integrity of high field-effect mobility of 477 cm2/V · s and good ON/OFF current ratio of 1.07 × 108.

Physical properties of ZnO thin films codoped with titanium and hydrogen prepared by RF magnetron sputtering with different substrate temperatures

Transparent conducting titanium-doped zinc oxide (TZO) thin films were prepared on glass substrates by RF magnetron sputtering using 1.5 wt% TiO2-doped ZnO as the target. Electrical, structural, and optical properties of films were investigated as a function of H2/(Ar + H2) flow ratios (RH) and substrate temperatures (TS). The optimal RH value for achieving high conducting TZO:H thin film decreased from 10% to 1% when TS increased from RT to 300°C. The lowest resistivity of 9.2 × 10-4 Ω-cm was obtained as TS = 100°C and RH = 7.5%. X-ray diffraction patterns showed that all of TZO:H films had a hexagonal wurtzite structure with a preferred orientation in the (002) direction. Atomic force microscopy analysis revealed that the film surface roughness increased with increasing RH. The average visible transmittance decreased with increasing RH for the RT-deposited film, while it had not considerably changed with different RH for the 300°C-deposited films. The optical bandgap increased as RH increased, which is consistent with the Burstein-Moss effect. The figure of merits indicated that TS = 100°C and RH = 7.5% were optimal conditions for TZO thin films as transparent conducting electrode applications.

Poly Si Nanowire Thin Film Transistors With Vacuum Gap Design

Via a simple selective-etching technique, a poly Si nanowire (NW) thin-film transistor (TFT), accompanied with the offset region, embedded vacuum gaps, and subgate structure, has been fabricated and characterized. The embedded vacuum gaps serves as an effective thicker insulator above the offset region, thus effectively reduces OFF-state leakage current and kink effect. This is because, under gate/drain biases, the electric field at channel surface near the drain can be reduced by the vacuum gap design compared with that in the conventional NW TFT. The extension of TiN layer above vacuum gap serves as a subgate and induces an inversion layer at the offset region to maintain a high on-current. The local electrical field located at the channel spacer surface and sharp corner near the drain is much lower in proposed vacuum gap structure compared with that in conventional NW TFT. Therefore, the device reliability, such as the degradation of threshold voltage, subthreshold swing, and transconductance under dc hot-carrier stress, is obviously improved by the proposed vacuum gap structure. Therefore, this proposed NW TFT is suitable for applications in advanced system-on-panel and 3-D circuit.

A Novel Self-Aligned Double-Channel Polysilicon Thin-Film Transistor

In this paper, a high-current self-aligned double-channel polycrystalline silicon thin-film transistor (SA-DCTFT) is proposed, demonstrated, and analyzed. This self-aligned device, which includes two channels, a nitride spacer, two offset-gated structures, and a raised source/drain (RSD) region, reveals better device performance. In addition, the top and bottom channels of the proposed device are self-aligned, and no extra mask is needed as compared with the conventional double-channel devices. Our experimental results show that the on-current of the SA-DCTFT is about twice higher than that of the conventional structure, and the leakage current and kink effect are considerably reduced simultaneously. Moreover, the device stability, such as threshold voltage shift and current degradation under a high gate bias, is enhanced by the proposed self-aligned double channels, nitride spacer, offset-gated structures, and RSD design. The lower drain electric field of the SA-DCTFT is also benefitted to the device scaling down for better performance.

Gate Bias Stresses of Gate-All-Around Poly-Si TFTs With Multiple Nanowire Channels

Gate-all-around (GAA) poly-Si thin-film transistors (TFTs) with multiple nanowire channels has better performance compared with planar TFT, such as lower threshold voltage VTH, smaller subthreshold swing (SS), lower minimum current I OFF, higher maximum on/off current ratio ION/IOFF, and higher mobility. However, each nanowire has three sharp corners to obtain high local electric fields under gate bias stresses, such that GAA TFT inherently suffers from an inevitable reliability problem. The local electric fields accelerate the degradation of VTH and SS. The VTH degradation under negative gate bias stress is related to the released electron trapping in stressed gate oxide during diffusion-controlled electrochemical reaction. For GAA TFT, minimum IOFF and ION/IOFF ratio still maintain better characteristics due to smaller channel body. Moreover, the obvious retardation in mobility degradation was obtained for GAA TFT because the hydrogen atoms can effectively rearrange the tail states located near the band edge in the channel during gate bias stresses.

Resistance switching behavior of ZnO resistive random access memory with a reduced graphene oxide capping layer

In this work, we investigate the characteristics of ZnO resistive random access memory (RRAM) with a reduced graphene oxide (rGO) capping layer and the polarity effect of the SET/RESET bias on the RRAM. The rGO film insertion enhances the stability of the current–voltage (I–V) switching curve and the superior resistance ratio (~105) of high-resistance state (HRS) to low-resistance state (LRS). Using the appropriate polarity of the SET/RESET bias applied to the rGO-capped ZnO RRAM enables the oxygen ions to move mainly at the interface of the rGO and ZnO films, resulting in the best performance. Presumably, the rGO film acts as an oxygen reservoir and enhances the easy in and out motion of the oxygen ions from the rGO film. The rGO film also prevents the interaction of oxygen ions and the Al electrode, resulting in excellent performance. In a pulse endurance test, the rGO-capped ZnO RRAM reveals superior endurance of up to 108 cycles over that of the ZnO RRAM without rGO insertion (106 cycles).

Gate-all-around polycrystalline-silicon thin-film transistors with self-aligned grain-growth nanowire channels

In this letter, gate-all-around (GAA) polycrystalline silicon thin-film transistors (TFTs) with self-aligned grain-growth channels were fabricated using excimer laser crystallization (ELC) on a recessed-nanowire (RN) structure. Via the RN structure constructed by a simple sidewall-spacer formation, location-controlled nucleation and volume-confined lateral grain growth within the RN body during ELC process have been demonstrated with only one perpendicular grain boundary in each nanowire channel. Because of the high-crystallinity channel together with GAA operation mode, the proposed GAA-RN TFTs show good device integrity of lower threshold voltage, steeper subthreshold slope, and higher field-effect mobility as compared with the conventional planar counterparts.

Effect of Nitrogen Plasma Treatment on Electrical Characteristics for Pd Nanocrystals in Nonvolatile Memory

Pd nanocrystals (NCs) are successfully embedded in a TaN/SiO2/HfAlO/Si structure. The initial memory window increases at a higher rate with increasing fabrication temperature of Pd NCs compared with the linear variation of Pd NC density, which is related to the thermally induced neutral traps in the HfAlO film around Pd NCs. After manufacturing a TaN/SiO2/Pd NCs/HfAlO/Si/Al structure, the subsequent N2 plasma treatment is conducted at 300 °C for 3 min. The number of leakage current paths in the SiO2 blocking layer adjacent to TaN is clearly reduced, but that of leakage current paths in SiO2/HfAlO around Pd NCs is slightly increased owing to the thermal stress. The thermally induced neutral traps in the HfAlO film around the Pd NCs can be passivated by nitrogen atoms, which leads to the improvement of the final memory window for the Pd NC samples fabricated at 600–700 °C. However, the intrinsic traps in the HfAlO film play an important role in memory characteristic and the final memory window is reduced by thermal densification for the Pd NC samples fabricated at 500 °C.